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rev. 1.11 5/09 copyright ? 2009 by silicon laboratori es si3050 + si3011 si3050 + si3011 fcc/tbr21 v oice daa features applications description the si3050+si3011 voice daa chipset provides a highly-programmable foreign exchange office (fxo) analog interfac e that is ideal for dsl iads, pbxs, ip-pbxs, and voip gateway products . the solution implements silicon laboratories' patented isolation capacito r technology, which eliminates the need for costly isolation transformers, relays, or opto-isolators, while providing superior surge immunity for robust field performance. the voice daa is available in one 20-pin tssop (si3050) and one 16-pin tssop/soic (si3011) and requires minimal external components. the si3050 interfaces directly to standard telephony pcm interfaces. functional block diagram ? pcm highway data interface ? -law/a-law companding ? spi control interface ? gci interface ? 80 db dynamic range tx/rx ? line voltage monitor ? loop current monitor ? +6 dbm tx/rx level mode ? parallel handset detection ? 3 a on-hook line monitor current ? overload detection ? programmable ac termination ? tip/ring polar ity detection ? integrated codec and 2- to 4-wire analog hybrid ? programmable digital hybrid for near-end echo reduction ? polarity reversal detection ? programmable digital gain in 0.1 db increments ? integrated ring detector ? type i and ii caller id support ? pulse dialing support ? 3.3 v power supply ? daisy-chaining for up to 16 devices ? greater than 5000 v isolation ? patented isolation technology ? ground start and loop start support ? available in pb-free rohs-compliant packages ? dsl iads ? voip gateways ? pbx and ip-pbx systems ? voice mail systems hybrid, ac and dc terminations ring detect off-hook ib sc dct vreg2 dct2 dct3 rng1 rng2 qb qe qe2 rx si3011 vreg si3050 control data interface isolation interface cs sclk sdi sdo sdi thru control logic pclk dtx drx fsync line data interface rg tgd tgde reset aout/int rgdt isolation interface us patent# 5,870,046 us patent# 6,061,009 other patents pending ordering information see page 96. pin assignments si3050 si3011 2 1 3 4 5 6 7 8 15 16 14 13 12 11 9 10 19 20 18 17 fsync sclk pclk sdi sdo aout/int rg dtx drx v a c1a c2a sdithru reset gnd tgde tgd cs rgdt v dd qe dct rx ib c1b c2b vreg rng1 dct2 dct3 qb qe2 sc vreg2 rng2 ignd 2 1 3 4 5 6 7 8 15 16 14 13 12 11 10 9
si3050 + si3011 2 rev. 1.11
si3050 + si3011 rev. 1.11 3 t able of c ontents section page 1. electrical specificat ions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 2. typical application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3. bill of materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4. aout pwm output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 5. functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 5.1. line-side device support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.2. power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.3. initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 5.4. isolation barrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 5.5. power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.6. calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.7. in-circuit testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.8. exception handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.9. revision identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.10. transmit/receive full-sca le level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.11. parallel handset detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.12. line voltage/loop current sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.13. off-hook . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 5.14. ground start support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.15. interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.16. dc termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.17. ac termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.18. ring detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 6 5.19. ring validation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 7 5.20. ringer impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.21. pulse dialing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.22. receive overload detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 5.23. billing tone filter (optional ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.24. on-hook line moni tor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.25. caller id . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.26. overload detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 5.27. gain control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.28. transhybrid balance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.29. filter selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.30. clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.31. communication interface mode sele ction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 5.32. pcm highway . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.33. companding in pcm mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 5.34. 16 khz sampling operation in pc m mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 5.35. spi control interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 5.36. gci highway . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
si3050 + si3011 4 rev. 1.11 5.37. companding in gci mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 5.38. 16 khz sampling operati on in gci mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 5.39. monitor channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 5.40. summary of monitor channel comm ands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 5.41. device address byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 5.42. command byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 5.43. register address byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 5.44. sc channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1 5.45. receive sc channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 5.46. transmit sc channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 6. control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 appendix?iec/ul60950 3rd edition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 7. pin descriptions: si3050 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 8. pin descriptions: si3011 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 9. ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 10. product identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 11. package outline: 20-pi n tssop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 12. package outline: 16-pin soic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 13. package outline: 16-pi n tssop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 silicon labs si3050 support documentatio n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 document change list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5 contact information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106
si3050 + si3011 rev. 1.11 5 1. electrical specifications table 1. recommended operating conditions and thermal information parameter 1 symbol test condition min 2 typ max 2 unit ambient temperature t a f-grade 0 25 70 c g-grade ?40 25 85 si3050 supply voltage, digital v d 3.0 3.3 3.6 v thermal resistance (si3011) 3 ? ja soic-16 ? 77 ? c/w tssop-16 ? 89 ? c/w thermal resistance (si3050) 3 ? ja tssop-20 ? 84 ? c/w notes: 1. the si3050 specifications are guaranteed when the typical application circuit (i ncluding component tolerance) and any si3050 and any si3011 are used. see "2. typical application schematic" on page 17 for the typical application circuit. 2. all minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. typical values apply at nominal supply voltages and an operating temperature of 25 c unless otherwise stated. 3. operation above 125 c junction temper ature may degrade device reliability.
si3050 + si3011 6 rev. 1.11 figure 1. test circuit for loop characteristics table 2. loop characteristics (v d = 3.0 to 3.6 v, t a = 0 to 70 c for k-grade, see figure 1 on page 6) parameter symbol test condition min typ max unit dc termination voltage v tr i l = 20 ma, ilim = 0 dcr = 0 ??7.5v dc termination voltage v tr i l = 120 ma, ilim = 0 dcr = 0 9??v dc termination voltage v tr i l = 20 ma, ilim = 1 dcr = 0 ??7.5v dc termination voltage v tr i l = 60 ma, ilim = 1 dcr = 0 40 ? ? v dc termination voltage v tr i l = 50 ma, ilim = 1 dcr = 0 ??40 v on-hook leakage current i lk v tr =?48v ? ? 5 a operating loop current i lp ilim = 0 10 ? 120 ma operating loop current i lp ilim = 1 10 ? 60 ma dc ring current dc current flowing through ring detection circuitry ?1.5 3 a ring detect voltage * v rd rt2 = 0 13.5 15 16.5 v rms ring frequency f r 13 ? 68 hz ringer equivalence number ren ? ? 0.2 *note: the ring signal is guaranteed to not be detected below the minimum. the ring signal is guaranteed to be detected above the maximum. tip ring + ? si3011 v tr i l 10 ?? f 600 ?
si3050 + si3011 rev. 1.11 7 table 3. dc characteristics, v d = 3.3 v (v d = 3.0 to 3.6 v, t a = 0 to 70 c for f/k-grade) parameter symbol test condition min typ max unit high level input voltage 1 v ih 2.0 ? ? v low level input voltage 1 v il ??0.8v high level output voltage v oh i o =?2ma 2.4 ? ? v low level output voltage v ol i o = 2 ma ? ? 0.35 v aout high level voltage v ah i o =10ma 2.4 ? ? v aout low level voltage v al i o =10ma ? ? 0.35 v input leakage current i l ?10 ? 10 a power supply cu rrent, digital 2 i d v d pin ? 8.5 10 ma total supply current, sleep mode 2 i d pdn = 1, pdl = 0 ? 5.0 6.0 ma total supply current, deep sleep 2,3 i d pdn = 1, pdl = 1 ? 1.3 1.5 ma notes: 1. v ih /v il do not apply to c1a/c2a. 2. all inputs at 0.4 or v d ? 0.4 (cmos levels). all inputs are held st atic except clock and all outputs unloaded (static i out = 0ma). 3. rgdt is not functional in this state.
si3050 + si3011 8 rev. 1.11 table 4. ac characteristics (v d = 3.0 to 3.6 v, t a = 0 to 70 c for f/k-grade, fs = 8000 hz, see "2. typical application schematic" on page 17 ) parameter symbol test condition min typ max unit sample rate fs 8 ? 16 khz pclk input frequency pclk 256 ? 8192 khz receive frequency response low ?3 dbfs corner, filt = 0 ? 5 ? hz receive frequency response low ?3 dbfs corner, filt = 1 ? 200 ? hz transmit full-scale level 1 v fs full2=1(+6.0dbm) 2 ?2.16?v peak receive full-scale level 1,3 v fs full2=1(+6.0dbm) 2 ?2.16?v peak dynamic range 4,5,6 dr ilim = 1, full2 = 0 dcr = 0, i l = 20, 50, 100 ma ?80?db receive total harmonic distortion 6,7 thd ilim = 1, full2 = 0 dcr = 0, i l =20, 50ma ??78? db receive total harmonic distortion 6,7 thd ilim = 1, full2 = 0 dcr = 0, i l = 100 ma ??72? db dynamic range (caller id mode) 8 dr cid vin= 1khz, ?13dbfs ? 62 ? db caller id full-scale level 8 v cid ?1.5?v peak gain accuracy 6,9 2-w to dtx, txg2, rxg2, txg3, and rxg3 = 0000 ?0.5 0 0.5 db transhybrid balance 10 300?3.4 khz, z acim = z line 20 ? ? db transhybrid balance 10 1khz, z acim = z line ?30?db two-wire return loss 300?3.4 khz, all ac terminations 25 ? ? db two-wire return loss 1 khz, all ac terminations ? 32 ? db notes: 1. measured at tip and ring with 600 ?? termination at 1 khz, as shown in figure 1 on page 6. 2. with full2 = 1, the transmit and receive full-scale level of +6.0 dbm can be achieved with a 600 ? termination. in this mode, the daa will transmit and receive +1.5 dbv into all reference impedances. 3. receive full-scale level produces ?0.9 dbfs at dtx. 4. dr = 20 x log (rms v fs /rms vin) + 20 x log (rms v in /rms noise). the rms noise measurement excludes harmonics. here, v fs is the 0 dbm full-scale level per note 1 above. 5. measurement is 300 to 3400 hz. applies to both transmit and receive paths. 6. vin=1khz, ?3dbfs. 7. thd = 20 x log (rms distortion/rms signal). 8. dr cid = 20 x log (rms v cid /rms v in ) + 20 x log (rms v in /rms noise). v cid is the 1.5 v full-scale level with the enhanced caller id circuit. with the typical cid circuit, the v cid full-scale level is 6 v peak, and the dr cid decreases to 50 db. 9. refer to tables 10?11 for relative gain accuracy characteristics (passband ripple). 10. analog hybrid only. z acim controlled by acim in register 30.
si3050 + si3011 rev. 1.11 9 table 5. absolute maximum ratings parameter symbol value unit dc supply voltage v d ?0.5 to 3.6 v input current, si3050 digital input pins i in 10 ma digital input voltage v ind ?0.3 to (v d + 0.3) v ambient operating temperature range t a ?40 to 100 c storage temperature range t stg ?65 to 150 c note: permanent device damage can occur if the above absolute maximum ratings are exceeded. functional operation should be restricted to the conditions as specified in the operational sections of this data sheet. exposure to absolute maximum rating conditions for extended periods might affect device reliability.
si3050 + si3011 10 rev. 1.11 figure 2. general inputs timing diagram table 6. switching characteristics?general inputs (v d = 3.0 to 3.6 v, t a = 0 to 70 c for k-grade, c l = 20 pf) parameter 1 symbol min typ max unit cycle time, pclk t p 0.12207 ? 3.90625 ? s pclk duty cycle t dty 40 50 60 % pclk jitter tolerance t jitter ?? 2 ns rise time, pclk t r ?? 25ns fall time, pclk t f ?? 25ns pclk before reset ? 2 t mr 10 ? ? cycles reset pulse width 3 t rl 250 ? ? ns cs , sclk before reset ? t mxr 20 ? ? ns rise time, reset t r ?? 25ns notes: 1. all timing (except rise and fall time) is referenced to the 50% level of the waveform. input test levels are v ih = v d ? 0.4 v, v il = 0.4 v. rise and fall times are referenced to the 20% and 80% levels of the waveform. 2. fsync/pclk relationship must be fixed after reset ?? 3. the minimum reset pulse width is the greater of 250 ns or 10 pclk cycle times. pclk t f t mr t p t r v ih v il t rl reset t mxr cs, sclk
si3050 + si3011 rev. 1.11 11 figure 3. spi timing diagram table 7. switching characteristics?serial peripheral interface (v io = 3.0 to 3.6 v, t a = 0 to 70 c for k-grade, c l = 20 pf) parameter* symbol test conditions min typ max unit cycle time sclk t c 61.03 ? ? ns rise time, sclk t r ? ? 25 ns fall time, sclk t f ? ? 25 ns delay time, sclk fall to sdo active t d1 ? ? 20 ns delay time, sclk fall to sdo transition t d2 ? ? 20 ns delay time, cs rise to sdo tri-state t d3 ? ? 20 ns setup time, cs to sclk fall t su1 25 ? ? ns hold time, sclk to cs rise t h1 20 ? ? ns setup time, sdi to sclk rise t su2 25 ? ? ns hold time, sclk rise to sdi transition t h2 20 ? ? ns delay time between chip selects t cs 220 ? ? ns propagation delay, sdi to sdithru ? 6 ? ns *note: all timing (except rise and fall time) is referenced to the 50% level of the waveform. input test levels are v ih =v d ? 0.4 v, v il = 0.4 v. rise and fall times are referenced to the 20% and 80% levels of the waveform. sdo sdi sclk t su1 t su2 t h2 t d2 t d1 t d3 t h1 cs t f t r t c t cs
si3050 + si3011 12 rev. 1.11 figure 4. pcm highway interface timing diagram (rxs = txs = 1) table 8. switching characteristics?pcm highway serial interface (v d = 3.0 to 3.6 v, t a = 0 to 70 c for k-grade, c l = 20 pf) parameter 1 symbol test conditions min typ max units cycle time pclk t p 122 ? 3906 ns valid pclk inputs ? ? ? ? ? ? ? ? 256 512 768 1.024 1.536 2.048 4.096 8.192 ? ? ? ? ? ? ? ? khz khz khz mhz mhz mhz mhz mhz fsync period 2 t fp ?125? ? s pclk duty cycle t dty 40 50 60 % pclk jitter-tolerance t jitter ??2ns fsync jitter tolerance t jitter ? ? 120 ns rise time, pclk t r ? ? 25 ns fall time, pclk t f ? ? 25 ns delay time, pclk rise to dtx active t d1 ? ? 20 ns delay time, pclk rise to dtx transition t d2 ? ? 20 ns delay time, pclk rise to dtx tri-state 3 t d3 ? ? 20 ns setup time, fsync rise to pclk fall t su1 25 ? ? ns hold time, pclk fall to fsync fall t h1 20 ? ? ns setup time, drx transition to pclk fall t su2 25 ? ? ns hold time, pclk falling to drx transition t h2 20 ? ? ns notes: 1. all timing is referenced to the 50% level of the waveform. input test levels are v ih =v o ? 0.4 v, v il = 0.4 v, rise and fall times are referenced to the 20% and 80% levels of the waveform. 2. fsync must be 8 khz under all operating conditions. 3. specification applies to pclk fall to dt x tri-state when that mode is selected. t su1 t h1 t p t su2 t h2 t d3 t d2 t d1 pclk fsync drx dtx t fp
si3050 + si3011 rev. 1.11 13 figure 5. gci highway interface timing diagram (1x pclk mode) table 9. switching characteristics?gci highway serial interface (v d = 3.0 to 3.6 v, t a = 0 to 70 c for k-grade, c l = 20 pf) parameter 1 symbol test conditions min typ max units cycle time pclk (single clocking mode) t p ?488?ns cycle time pclk (double clocking mode) t p ?244?ns valid pclk inputs ? ? 2.048 4.096 ? ? mhz mhz fsync period 2 t fp ?125?s pclk duty cycle t dty 40 50 60 % pclk jitter tolerance t jitter ?? 2ns fsync jitter tolerance t jitter ??120ns rise time, pclk t r ??25ns fall time, pclk t f ??25ns delay time, pclk rise to dtx active t d1 ??20ns delay time, pclk rise to dtx transition t d2 ??20ns delay time, pclk rise to dtx tri-state 3 t d3 ??20ns setup time, fsync rise to pclk fall t su1 25 ? ? ns hold time, pclk fall to fsync fall t h1 20 ? ? ns setup time, drx transition to pclk fall t su2 25 ? ? ns hold time, pclk falling to drx transition t h2 20 ? ? ns notes: 1. all timing is referenced to the 50% level of the waveform. input test levels are v ih = v o ? 0.4 v, v il = 0.4 v, rise and fall times are referenced to the 20% and 80% levels of the waveform. 2. fsync must be 8 khz under all operating conditions. 3. specification applies to pclk fall to dt x tri-state when that mode is selected. t p t r t f t su2 t h2 t d3 t d2 t d1 pclk fsync drx dtx t fp t h1 t su1
si3050 + si3011 14 rev. 1.11 figure 6. gci highway interface timing diagram (2x pclk mode) table 10. digital fir filter characteristics?transmit and receive (v d = 3.0 to 3.6 v, sample rate = 8khz, t a = 0 to 70 c for k-grade) parameter symbol min typ max unit passband (0.1 db) f (0.1 db) 0?3.3khz passband (3 db) f (3 db) 0?3.6khz passband ripple peak-to-peak ?0.1 ? 0.1 db stopband ? 4.4 ? khz stopband attenuation ?74 ? ? db group delay t gd ? 12/fs ? s note: typical fir filter characteristics for fs = 8000 hz are shown in figures 7, 8, 9, and 10. table 11. digital iir filter characteristics?transmit and receive (v d = 3.0 to 3.6 v, sample rate = 8khz, t a = 0 to 70 c for k-grade) parameter symbol min typ max unit passband (3 db) f (3 db) 0?3.6khz passband ripple peak-to-peak ?0.2 ? 0.2 db stopband ? 4.4 ? khz stopband attenuation ?40 ? ? db group delay t gd ? 1.6/fs ? s note: typical iir filter ch aracteristics for fs = 8000 hz are shown in figures 11, 12, 13, and 14. figures 15 and 16 show group delay versus input frequency. pclk fsync drx dtx t r t f t d1 t su2 t h2 t h1 t fp t su2 t d2 t d3
si3050 + si3011 rev. 1.11 15 figure 7. fir receive filter response figure 8. fir receive filter passband ripple figure 9. fir transmit filter response figure 10. fir transmit filter passband ripple for figures 7?10, all filter plots apply to a sample rate of fs = 8khz. for figures 11?14, all filter plots apply to a sample rate of fs = 8khz.
si3050 + si3011 16 rev. 1.11 figure 11. iir receive filter response figure 12. iir receive filter passband ripple figure 13. iir transmit filter response figure 14. iir transmit filter passband ripple figure 15. iir receive group delay figure 16. iir transmit group delay
si3050 + si3011 rev. 1.11 17 2. typical application schematic vdd /int /rg fsync /tgd /tgde /reset /rgdt pclk drx dtx sdi sdithru sclk sdo /cs ring tip pcm highway spi control ground start no ground plane in daa section opti onal cid population q3 u1 si3050 sdo 1 sdi 2 cs 3 fsync 4 pclk 5 dtx 6 drx 7 rgdt 8 rst 13 c2a 14 c1a 15 va 16 vdd 17 gnd 18 sclk 19 sdi_thru 20 aout/int 9 rg 10 tgde 12 tgd 11 rv1 r11 c51 r31 -+ d1 u2 si301 1 qe 1 dct 2 rx 3 ib 4 c1b 5 c2b 6 vreg 7 rng1 8 dct2 16 ignd 15 dct3 14 qb 13 qe2 12 sc 11 vreg2 10 rng2 9 r3 r32 r302 fb1 r13 r10 r30 c1 fb2 r52 c9 + c4 q4 r9 r53 r6 q1 c6 r5 r12 r16 c50 c30 c2 r33 q5 q2 r15 z1 c7 c31 r8 r2 r4 c3 c10 c8 r7 r1 r51 c5 fiure 17 typical application circuit or te si3050 and si3011 reer to an67 si3050/52/54/56 layout guidelines or recoended layout guidelines
si3050 + si3011 18 rev. 1.11 3. bill of materials component value supplier(s) c1, c2 33 pf, y2, x7r, 20% panasonic, murata, vishay c3 1 3.9 nf, 250 v, x7r, 20% venkel, smec c4 1.0 f, 50 v, elec/tant, 20% panasonic c5, c6, c50, c51 0.1 f, 16 v, x7r, 20% venkel, smec c7 2.7 nf, 50 v, x7r, 20% venkel, smec c8, c9 680 pf, y2, x7r, 10% panasonic, murata, vishay c10 0.01 f, 16 v, x7r, 20% venkel, smec c30, c31 1 120 pf, 250 v, x7r, 10% venkel, smec d1, d2 2 dual diode, 225 ma, 300 v, (cmpd2004s) central semiconductor fb1, fb2 ferrite bead, blm18ag601sn1 murata q1, q3 npn, 300 v, mmbta42 central onsemi, fairchild q2 pnp, 300 v, mmbta92 c entral onsemi, fairchild q4, q5 npn, 80 v, 330 mw, mmbta06 central onsemi, fairchild rv1 sidactor, 275 v, 100 a teccor, diodes inc., shindengen r1 1.07 k ? , 1/2 w, 1% venkel, smec, panasonic r2 150 ? , 1/16 w, 5% venkel, smec, panasonic r3 3.65 k ? , 1/2 w, 1% venkel, smec, panasonic r4 2.49 k ? , 1/2 w, 1% venkel, smec, panasonic r5, r6 100 k ? , 1/16 w, 5% venkel, smec, panasonic r7, r8 1 not installed, 20 m ? , 1/8 w, 5% venkel, smec, panasonic r9 1 m ? , 1/16 w, 1% venkel, smec, panasonic r10 536 ? , 1/4 w, 1% venkel, smec, panasonic r11 73.2 ? , 1/2 w, 1% venkel, smec, panasonic r12, r13 3 0 ? , 1/16 w venkel, smec, panasonic r15, r16 4 0 ? , 1/16 w venkel, smec, panasonic r30, r32 1 15 m ? , 1/8 w, 5% venkel, smec, panasonic r31, r33 1 5.1 m ? , 1/8 w, 5% venkel, smec, panasonic r51, r52, r53 4.7 k ? , 1/16 w, 5% ? venkel, smec, panasonic u1 si3050 silicon labs u2 si3011 silicon labs z1 zener diode, 43 v, 1/2 w general semi, on semi, diodes inc. notes: 1. r7?r8 may be substituted for r30?r33 and c30?c31 for lower cost, but reduced cid performance. 2. several diode bridge configurations are acceptable. parts, such as a single hd04, a df-04s, or four 1n4004 diodes, may be used (suppliers include general semiconductor, diodes inc., etc.). 3. 56 ? , 1/16, 1% resistors may be substituted for r12?r13 (0 ? ) to decrease emissions. (see an81.) 4. murata blm18ag601sn1 may be substituted for r15?r16 (0 ? ) to decrease emissions. (see an81.)
si3050 + si3011 rev. 1.11 19 4. aout pwm output figure 18 illustrates an optional circui t to support the pulse width modulati on (pwm) output capability of the si3050 for call progress monitoring purposes.to enable this mode, the inte bit (register 2) should be set to 0, the pwme bit (register 1) set to 1, and the pwmm bits (register 2) set to 00. figure 18. aout pwm circuit for call progress registers 20 and 21 allow the receive and transmit paths to be attenuated linearly. when these registers are set to all 0s, the transmit and receive paths are muted. these registers affect the call progress output only and do not affect transmit and receive operations on the telephone line. the pwmm[1:0] bits (register 1, bits 5:4 ) select one of three different pwm output modes for the aout signal, including a delta-sigma data stream, a 32 khz return to 0 pwm output, and a balanced 32 khz pwm output. table 12. component values?aout pwm component value supplier ls1 speaker brt1209pf-06 intervox q6 npn ksp13 fairchild c41 0.1 f, 16 v, x7r, 20% venkel, smec r41 150 ??? 1/10 w, 5% venkel, smec, panasonic aout +5va r41 ls1 q6 c41
si3050 + si3011 20 rev. 1.11 5. functional description the si3050 is an integrated direct access arrangement (daa) providing a programmable line interface that meets global telephone line requirements. the si3050 implements silicon laborato ries? patented isolation capacitor technology, which offers the highest level of integration by replacing an analog front end (afe), an isolation transformer, relays, opto-isolators, and a 2- to 4-wire hybrid with two highly-integrated ics. the si3050+si3011 chipset is software programmable and designed to meet fcc and tbr21 specifications. in addition, the si3050 meets the most stringent global requirements for out-of-band energy, emissions, immunity, high-voltage surges, and safety, including fcc parts 15 and 68, en55022, en55024, and many other standards. 5.1. line-side device support three different line-side devices are available for use with the si3050 system-side device. this data sheet covers the si3011, which has been optimized for tbr21 and fcc-compliant countries. for information on a globally-compliant solution, refer to the si3050-si3018/ 19 data sheet. 5.2. power supplies the si3050 operates from a 3.3 v power supply. the si3050 input pins can only accept 3.3 v cmos signal levels. if support of 5 v si gnal levels is necessary, a level shifter is required. the si3011 derives its power from two sources: the si3050 and the telephone line. the si3050 supplies power over the patented isolation capacitor link between the two devices, allowing the si3011 to communicate with the si3050 while on-hook and perform other on-hook functions, such as line voltage monitoring. when off-hook, the si3011 also derives power from the line current supplied from the telephone line. this feature is exclusive to daas from silicon labs and allows the most cost-effective implementation for a daa wh ile still maintaining robust performance over all line conditions. 5.3. initialization each time the si3050 is powered up, assert the reset pin. when the reset pin is deasserted, the registers have default values to guarantee the line-side device (si3011) is powered down without the possibility of loading the line (i.e., off-hook ). an example initialization procedure follows: 1. power up and de-assert reset . 2. wait until the pll is locked. this time is less than 1 ms from the application of pclk. 3. enable pcm (register 33) or gci (register 42) mode. 4. set the desired line interfac e parameters (i.e., ilim, dcr, acim, ohs2, tga2, and txg2[3:0]). 5. set the full2 and iire bits as required. 6. write a 0x00 into register 6 to power up the line-side device. when this procedure is complete, the si3011 is ready for ring detection and off-hook operation. 5.4. isolation barrier the si3050 achieves an isolation barrier through low-cost, high-voltage capaci tors in conjunction with silicon laboratories? patented signal processing techniques. differential capacitive communication eliminates signal degradation from capacitor mismatches, common mode interference, or noise coupling. as shown in the "2. typical application schematic" on page 17, the c1, c2, c8, and c9 capacitors isolate the si3050 (system-side) from the si3011 (line-side). transmit, receive, control, ring detect, and caller id data are passed across this barrier. the communications link is disabled by default. to enable it, the pdl bit (register 6, bit 4) must be cleared. no communication between the si3050 and si3011 can occur until this bit is cleared. allow the pll to lock to the pclk and fsync input signals before clearing the pdl bit. 5.5. power management the si3050 supports four basic power management operation modes. the modes are normal operation, reset operation, sleep mode, and full powerdown mode. the power management modes are controlled by the pdn and pdl bits (register 6). on powerup, or following a reset, the si3050 is in reset operation. the pdl bit is set, and the pdn bit is cleared. the si3050 is operational, except for the communications link. no communication between the si3050 and line-side device (si3011) can occur during reset operation. bits associated with the line-side device are invalid in this mode. in typical applications, th e daa will predominantly be operated in normal mode. in normal mode, the pdl and pdn bits are cleared. the daa is operational and the communications link passes information between the si3050 and the si3011. the si3050 supports a low-power sleep mode that supports ring validation and wake-up-on-ring features. to enable the sleep mode, the pdn bit must be set.
si3050 + si3011 rev. 1.11 21 when the si3050 is in sleep mode, the pclk signal must remain active. in low-power sleep mode, the si3050 is non-functional ex cept for the communications link and the rgdt signal. to take the si3050 out of sleep mode, pulse the reset pin (reset ) low. in summary, the powerdown/up sequence for sleep mode is as follows: 1. ensure the pdl bit (register 6, bit 4) is cleared. 2. set the pdn bit (register 6, bit 3). 3. the device is now in sleep mode. pclk must remain active. 4. to exit sleep mode, reset the si3050 by pulsing the reset pin. 5. program registers to desired settings. the si3050 also supports an additional powerdown mode. when both the pdn (register 6, bit 3) and pdl (register 6, bit 4) bits are set, the chipset enters a complete powerdown mode and draws negligible current (deep sleep mode). in this mode, the si3050 is non-functional. the rgdt pin does not function and the si3050 will not detect a ring. normal operation can be restored using the same process for taking the si3050 out of sleep mode. 5.6. calibration the si3050 initiates two auto-calibrations by default when the device goes off-hook or experiences a loss of line power. a 17 ms resistor calibration is performed to allow circuitry internal to the daa to adjust to the exact line conditions present at the time of going off-hook. this resistor calibration can be disabled by setting the rcald bit (register 25, bit 5). a 256 ms adc calibration is also performed to remove offsets that might be present in the on-chip a/d converter, which could affect the a/d dynamic range. the adc auto-calibration is initiated after the daa dc termination stabilizes and the resistor ca libration completes. due to the large variation in lin e conditions and line card behavior presented to the daa, it might be beneficial to use manual adc calibration instead of auto-calibration. manual adc calibration should be executed as close as possible to 256 ms before valid transmit/receive data is expected. the following steps should be taken to implement manual adc calibration: 1. the cald bit (auto-calib ration disable?register 17) must be set to 1. 2. the mcal bit (manual calibration) must be toggled to one and then 0 to begin and complete the calibration. 3. the calibration is completed in 256 ms. 5.7. in-circuit testing the si3050?s advanced design provides the designer with an increased abilit y to determine system functionality during production line tests and support for end-user diagnostics. six loopback modes allow increased coverage of system components. for four of the test modes, a line-side power source is needed. while a standard phone line can be used, the test circuit in figure 1 on page 6 is adequate. in addition, an off-hook sequence must be performed to connect the power source to th e line-side device. for the start-up loopback test mode, no line-side power is necessary, and no off-hook sequence is required. the start-up test mode is enabl ed by default. when the pdl bit (register 6, bit 4) is set (the default case), the line side is in a powerdown mode, and the system-side is in a digital loopback mode. in this mode, data received on drx passes through the internal filters and is transmitted on dtx. this pa th introduces approximately 0.9 db of attenuation on th e drx signal received. the group delay of both transmit and receive filters exists between drx and dtx. clearing the pdl bit disables this mode, and the dtx data switches to the receive data from the line side. when the pdl bit is cleared, the fdt bit (register 12, bit 6) becomes active to indicate that successful communication between the line side and system side is established. this provides verification that the communications link is operational. the digital data loop-back mode offers a way to input data on the drx pin and have the identical data output on the dtx pin through bypassing the transmit and receive filters. setting the ddl bit (register 10, bit 0) enables this mode, which provides an easy way to verify communication between the host processor/dsp and the daa. no line-side power or off-hook sequence is required for this mode. the remaining test modes require an off-hook sequence to operate. the following sequence lists the off-hook requirements: 1. powerup or reset. 2. allow the internal pll to lock on pclk and fsync. 3. enable line-side by clearing pdl bit. 4. issue an off-hook command. 5. delay 402.75 ms for calibration to occur. 6. set desired test mode. the communications link digital loopback mode allows the host processor to provide a digital input test pattern on drx and receive that digital test pattern back on dtx. to enable this mode, set the idl bit (register 1, bit 1). the communications link is tested in this mode. the digital stream is deliv ered across the isolation capacitors, c1 and c2, of the "2. typical application
si3050 + si3011 22 rev. 1.11 schematic" on page 17, to the line-side device and returned across the same path. in this digital loopback mode, the 0.9 db attenuation and filter group delays also exist. the pcm analog loopback mode extends the signal path of the analog loopback mode. in this mode, an analog signal is driven from the line into the line-side device. this analog signal is converted to digital data and then passed across the communications link to the system-side device. the data passes through the receive filter, through the transmit filter, and is then passed across the communications link and sent back out onto the line as an analog signal. set the pcml bit (register 33, bit 7) to enable this mode. with the final testing mode, internal analog loopback, the system can test the operation of the transmit and receive paths on the line-side device and the external components in the "2. typical application schematic" on page 17. the host provides a digital test waveform on drx. data passes across the isolation barrier, is transmitted to and received from the line, passes back across the isolation barrier, and is presented to the host on dtx. clear the hbe bit (register 2, bit 1) to enable this mode. when the hbe bit is cleared, it produces a dc offset that affects the signal swing of the transmit signal. silicon laboratories recommends that the transmit signal be 12 db lower than normal tran smit levels. a lower level eliminates clipping from the dc offset that results from disabling the hybrid. it is assumed in this test that the line ac impedance is nominally 600 ?? note: all test modes are mutually exclusive. if more than one test mode is enabled concurrently, the results are unpredictable. 5.8. exception handling the si3050 can determine if an error occurs during operation. through the secondary frames of the serial link, the controlling dsp can read several status bits. the bit of highest importance is the frame detect bit (fdt, register 12, bit 6) which indicates that the system-side (si3050) and line-side (si3011) devices are communicating. during normal operation, the fdt bit can be checked before reading the bits that indicate information about the line side. if fdt is not set, the following bits related to the line side are invalid?rdt, rdtn, rdtp, lcs[4:0], lsid[1:0], revb[3:0], lvs[7:0], lcs2[7:0], rov, btd, dod, and ovl; the rgdt operation is also non-functional. following powerup and reset, the fdt bit is not set because the pdl bit (register 6 bit 4) defaults to 1. in this state, the isocap is not operating and no information about the line side can be determined. the user must provide a valid pclk and fsync to the system and clear the pdl bit to activate the isocap link. communication with the line-side device takes less than 10 ms to establish. 5.9. revision identification the si3050 provides information to determine the revision of the si3050 and/or the si3011. the reva[3:0] bits (register 11) identify the revision of the si3050, where 0101b denotes revisi on e. the revb[3:0] bits (register 13) identify the revision of the line-side device, where 0110b denotes revision f. 5.10. transmit/recei ve full-scale level the si3050 supports programmable maximum transmit and receive levels. the default signal level supported by the si3050 is 0 dbm into a 600 ? load. the si3050+si3011 chipset supports an enhanced full-scale mode that can be enabled by setting the full2 bit in register 30. with full2 = 1, the full-scale signal level increases to +6.0 dbm into a 600 ? load or 1.5 dbv into all reference impedances. the full-scale and enhanced full-scale modes provide the ab ility to trade off tx power and tx distortion for a peak signal. by using the programmable digital gain registers in conjunction with the enhanced full-scale signal level mode, a specific power level (+3.2 dbm for example) can be achieved across all act settings. 5.11. parallel handset detection the si3050 can detect a parallel handset going off-hook. when the si3050 is off-hook, the loop current can be monitored with the lcs or lcs2 bits. a significant drop in loop current signals a parallel handset going off-hook. if a parallel handset going off-hook causes the loop current to drop to 0, the lcs and lcs2 bits will read all 0s. additi onally, the drop-out detect (dod) bit will fire (and gene rate an interrupt if the dodm bit is set) indicating that the line-derived power supply has collapsed. the lvs bits also can be read when on- or off-hook to determine the line voltage. significant drops in line voltage can signal a parallel handset. for the si3050 to operate in parallel with another handset, the parallel handset must have a sufficiently high dc termination to support two off-hook daas on the same line. improved parallel handset operation can be achieved by changing the dc impedance from 50 ? to 800 ? .
si3050 + si3011 rev. 1.11 23 5.12. line voltage/ loop current sensing the 5-bit lcs[4:0] register reports loop current measurements when off-hook. an additional register is available to report loop current to a finer resolution (lcs2[7:0]). the lvs[7:0] register can be read when the chipset is on or off hook. these registers can be used to help determine th e following line conditions: ? when on-hook, detect if a line is connected. ? when on-hook, detect if a parallel phone is off-hook. ? when off-hook, detect if a parallel phone goes on or off-hook. ? detect if enough loop current is available to operate. ? when used in conjunction with the opd bit, detect if an overload condition exists. (see "5.26. overload detection" on page 31.) 5.12.1. line voltage measurement the si3050 reports line volt age with the lvs[7:0] bits (register 29) in both on- and off-hook states with a resolution of 1 v per bit. the accuracy of these bits is approximately 10%. bits 0 through 7 of this 8-bit signed number indicate the value of the line voltage in 2s complement format. bit 7 indicates the polarity of the tip/ring voltage. if the inte bit (register 2, bit 7) and the polm bit (register 3, bit 0) are set, a hardware interrupt is generated on the aout/int pin when bit 7 of the lvs register changes state. the edge-triggered interrupt is cleared by writing 0 to the poli bit (register 4, bit 0). the poli bit is set each time bit 7 of the lvs register changes state, and must be written to 0 to clear it. the default state of the lvs register forces the lvs[7:0] bits to 0 when the line voltage is 3 v or less. the lvfd bit (register 31, bit 0) disables this force-to-zero function and allows the lvs register to display non-zero values of 3 v and below. this register may display unpredictable values at line voltages between 0 to 2 v. at 0 v, the lvs register displays all 0s. figure 19. typical loop current lcs transfer function (ilim = 0) 0 3.3 6.6 9.9 13.2 16.5 19.8 23.1 26.4 33 36.3 39.6 42.9 46.2 49.5 52.8 56.1 59.1 62.7 66 69.3 72.6 75.9 79.2 127 82.5 85.8 89.1 92.4 95.7 99 102.3 loop current (ma) lcs bits 29.7 0 5 10 15 20 25 30 possible overload
si3050 + si3011 24 rev. 1.11 5.12.2. loop current measurement when the si3050 is off-hook, the lcs[4:0] bits measure loop current in 3.3 ma/bit resolution. with the lcs[4:0] bits, a user can detect another phone going off-hook by monitoring the dc loop current. the line current sense transfer function is shown in figure 19 and is detailed in table 13. the lcs and lcs2 bits report loop current down to the minimum operating loop current for the daa. below this threshold, the reported value of loop current is unpredictable. the minimum operating loop current of the si3050+si3011 chipset is 10 ma. when the lcs bits reach max value, the loop current sense overload interrupt bi t (register 4) fires. lcsoi firing however, does not necessarily imply that an overcurrent situation has occurred. an overcurrent situation in the daa is deter mined by the status of the opd bit (register 19). after the lcsoi interrupt fires, the opd bit should be checked to determine if an overcurrent situation exists. the opd bit indicates an overcurrent situation when loop current exceeds either 160 ma (ilim = 0) or 60 ma (ilim = 1), depending on the setting of the ilim bit (register 26). the lcs2 register also reports loop current in the off-hook state. this register has a resolution of 1.1 ma per bit. 5.13. off-hook the communication system generates an off-hook command by setting the oh bit (register 5, bit 0). this off-hook state seizes the line for incoming/outgoing calls. it also can be used for pulse dialing. with the oh bit at logic 0, negligible dc current flows through the hookswitch. when a logic 1 is written to the oh bit, the hookswitch tran sistor pair, q1 and q2, turn on. a termination impedance across tip and ring is applied and causes dc loop current to flow. the termination impedance has both an ac and a dc component. several events occur in the daa when the oh bit is set. there is a 250 s latency for the off-hook command to be communicated to the lin e-side device. when the line-side device goes off-hook, an off-hook counter forces a delay to allow line transients to settle before transmission or reception can occur. the off-hook counter time is controlled by the foh[1:0] bits (register 31, bits 6:5). the default setting for the off-hook counter time is 128 ms, but can be adjusted up to 512 ms or down to 64 or 8 ms. after the off-hook counter expires, a resistor calibration is performed for 17 ms to allow the daa internal circuitry to adjust to the ex act conditions present at the time of going off-hook. this resistor calibration can be disabled by setting the rcald bit (register 25, bit 5). after the resistor calibration is performed, an adc calibration is performed fo r 256 ms. this calibration helps to remove offset in the a/d sampling the telephone line. adc calibration can be disabled by setting the cald bit (register 17, bit 5). see "5.6. calibration" on page 21 for more information on automatic and manual calibration. silicon laboratories recomme nds that the resistor and the adc calibrations not be disabled except when a fast response is needed after going off-hook, such as when responding to a type ii caller-id signal. see "5.25. caller id" on page 29 for detailed information. to calculate the total time required to go off-hook and start transmission or reception, include the digital filter delay (typically 1.5 ms wit h the fir filter) in the calculation. 5.14. ground start support the si3050 daa supports lo op-start applications by default. it can also support ground-start applications with the rg, tgd, and tgde pins and the schematic shown in figure 20. the component values are listed in table 14. table 13. loop current transfer function lcs[4:0] condition 00000 insufficient line current for normal operation. use the dod bit (register 19, bit 1) to determine if a line is still connected. 00100 minimum line current for normal operation. 11111 loop current may be excessive. use the opd bit to determine if an overload condi- tion exists.
si3050 + si3011 rev. 1.11 25 figure 20. typical application circuit for ground start support on the si3050 5.14.1. ground start idle ensure the relay in series wit h tip is closed by clearing the tgoe bit (register 32, bit 1). this enables the daa to sense if the co grounds tip. set rg to 1 (register 32, bit 0) so that no current flows through the relay connecting ring to ground. 5.14.2. daa requests line seizure with tgoe set to zero, se ize the line by closing the relay in series with ri ng (clear the rg bit, register 32, bit 0). the co detects this current flowing on ring and grounds tip. this sets the tgd bit (register 32, bit 2). the daa may then be taken off-hook and the relay in series with ring opened (clear the rg bit). the call continues as in loop-start mode. 5.14.3. co requests line seizure in a normal on-hook state, the relay in series with tip should be closed, connecting the ?24 v isolated supply. the co grounds tip to request line seizure, causing current to flow. the opto-isolator u3 (see figure 20 on page 25) detects this current and sets the tgd bit (register 32, bit 2). this bit remains high as long as current is detected. the tgdi bit (register 4, bit 1) is a sticky bit, and remains high until cleared. a hardware interrupt on the aout/int can be made to occur when tip current begins to flow by enabling the tgdm bit (register 3, bit 1). clear the in terrupt by writing 0 to the tgdi bit (register 4 bit 1). the daa may then be taken off-hook and the call continued as in loop-start mode. 5.15. interrupts the aout/int pin can be used as a hardware interrupt pin by setting the inte bit (register 2, bit 7). when this bit is set, the analog output used for call progress monitoring is not available. the default state of this interrupt output pin is ac tive low, but active high operation can be enabled by setting the intp bit (register 2, bit 6). this pin is an open-drain output when the inte bit is set and requires a 4.7 k ? pullup or pulldown for correct operat ion. if multiple int pins are connected to a single input, the combined pullup or pulldown resistance should equal 4.7 k ??? bits 7?0 in register 3 and bit 1 in register 44 can be set to enable hardware interrupt sources. when one or more of these bits is set, the aout/int pin goes into an active state and stays active until the interrupts are serviced. if more than one hardware interrupt is enabled in register 3, use software polling to de termine the cause of the interrupts. register 4 and bit 3 of register 44 contain sticky interrupt flag bits. clea r these bits after servicing the interrupt. registers 43 and 44 contain the line current/voltage threshold interrupt. this interrupt is triggered when the measured line voltage or current in the lvs or lcs2 registers, as selected by the cvs bit (register 44, bit 2), crosses the threshold programmed into the cvt[7:0] bits. with the cvp bit, the interrupt can be programmed to occur when the measured value rises above or falls below the threshold. only the magnitude of the measured value is used for comparison to the threshold programmed into the cvt[7:0] bits. therefore, only positive numbers should be used as a threshold. table 14. component values for the ground start support schematic symbol value supplier(s) r101 200 ? , 2 w, 5% venkel, smec, panasonic r102, r103, r106 1k ? , 1/10 w, 5% venkel, smec, panasonic r104 1.5 k ? , 1/10 w, 5% venkel, smec, panasonic r105 10 k ? , 1/2 w, 5% venkel, smec, panasonic rl1 aqw210s aromat, nec u3 ps2501l-1 nec, fairchild vd -24v vd tip ring tgdb rgb tgdeb rl1 opto-relay 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 u3 opto-isolator 1 1 2 2 3 3 4 4 r105 r101 r102 r103 r104 r106
si3050 + si3011 26 rev. 1.11 5.16. dc termination the si3050+si3011 chipset has programmable settings for the dc impedance and current limit. the dc impedance of the daa is normally represented with a 50 ? slope as shown in figure 21, but can be changed to an 800 ? slope by setting the dcr bit. this higher dc termination presents a higher resistance to the line as loop current increases. figure 21. fcc mode i/v characteristics for applications requiring cu rrent limiting per the tbr21 standard, the ilim bit may be set to select this mode. in this mode, the dc i/v curve is changed to a 2000 ? slope above 40 ma, as shown in figure 22. this allows the daa to operate with a 50 v, 230 ? feed, which is the maximum linefeed specified in the tbr21 standard. figure 22. tbr21 mode i/v characteristics 5.17. ac termination the si3050+si3011 chipset provides two ac termination impedances. the acim bit in register 30 is used to select the ac impedance setting. the two available settings for the si3050+si3011 chipset are listed in table 15. the programmable digital hybrid can be used to further reduce near-end echo for each of the four listed ac termination settings. see "5.28. transhybrid balance" on page 32 for details. 5.18. ring detection the ring signal is resistivel y coupled from tip and ring to the rng1 and rng2 pins. the si3050 supports either full- or half-wave ring detection. with full-wave ring detection, the designer can detect a polarity reversal of the ring signal. see ?5.25.caller id? on page 29. the ring detection threshold is programmable with the rt2 bit (register 17, bit 4). the ring detector output can be monitored in three ways. the first method uses the rgdt pin. the second method uses the register bits, rdtp, rdtn, and rdt (register 5). the final method uses the dtx output. the ring detector mode is controlled by the rfwe bit (register 18, bit 1). when the rfwe bit is 0 (default mode), the ring detector operates in half-wave rectifier mode. in this mode, only positive ring signals are detected. a positive ring signal is defined as a voltage greater than the ring threshold across rng1-rng2. conversely, a negative ring signal is defined as a voltage less than the negative ring threshold across rng1-rng2. when the rfwe bit is 1, the ring detector operates in full-wave rectifier mode. in this mode, both positive and negative ring signals are detected. the first method to monitor ring detection output uses the rgdt pin. when the rgdt pin is used, it defaults to active low, but can be changed to active high by setting the rpol bit (register 14, bit 1). this pin is an open-drain output, and requires a 4.7 k ?? pullup or pulldown for correct operat ion. if multiple rgdt pins are connected to a single input, the combined pullup or pulldown resistance should equal 4.7 k ?? when the rfwe bit is 0, the rgdt pin is asserted when the ring signal is positive, which results in an output signal frequency equal to the actual ring frequency. when the rfwe bit is 1, the rgdt pin is asserted when the ring signal is positive or negative. 12 11 10 9 8 7 6 .01 .02 .03 .04 .05 .06 .07 .08 .09 .1 .11 loop current (a) fcc dct mode voltage across daa (v) 45 40 35 30 25 20 15 10 5 .015 .02 .025 .03 .035 .04 .045 .05 .055 .06 loop current (a) tbr21 dct mode voltage across daa (v) table 15. ac termination settings acim ac termination 0 600 ? 1 210 ? + (750 ? || 150 nf) and 275 ? + (780 ? || 150 nf)
si3050 + si3011 rev. 1.11 27 the output then appears to be twice the frequency of the ring waveform. the second method to monitor ring detection uses the ring detect bits (rdtp, rdtn, and rdt). the rdtp and rdtn behavior is based on the rng1-rng2 voltage. when the signal on rng1-rng2 is above the positive ring threshold, the rdtp bit is set. when the signal on rng1-rng2 is below the negative ring threshold, the rdtn bit is set. when the signal on rng1-rng2 is between these thresholds, neither bit is set. the rdt behavior is also based on the rng1-rng2 voltage. when the rfwe bit is 0, a positive ring signal sets the rdt bit for a period of time. when the rfwe bit is 1, a positive or negative ring signal sets the rdt bit. the rdt bit acts like a one shot. when a new ring signal is detected, the one shot is reset. if no new ring signals are detected prior to the one shot counter reaching 0, then the rdt bit clears. the length of this count is approximately 5 seconds. the rdt bit is reset to 0 by an off-hook event. if the rdtm bit (register 3, bit 7) is set, a hardware interrupt occurs on the aout/int pin when rdt is triggered. this interrupt can be cleared by writing to the rdti bit (register 4, bit 7). when the rdi bit (register 2, bit 2) is set, an interrupt occurs on both the beginning and end of the ring pulse as defined by the rto bits (register 23, bits 6:3). ring validation may be enabled when using the rdi bit. the third method to monitor detection uses the dtx data samples to transmit ring data. if the isocap is active (pdl=0) and the device is not off-hook or in on-hook line monitor mode, the ring data is presented on dtx. the waveform on dtx depends on the state of the rfwe bit. when rfwe is 0, dtx is ?32768 (0x8000) while the rng1-rng2 voltage is between the thresholds. when a ring is detected, dtx transitions to +32767 when the ring signal is positive, then goes back to ?32768 when the ring is near 0 and negative. thus a near square wave is presented on dtx that swings from ?32768 to +32767 in cadence with the ring signal. when rfwe is 1, dtx sits at approximately +1228 while the rng1-rng2 voltage is between the thresholds. when the ring becomes positive, dtx transitions to +32767. when the ring signal goes near 0, dtx remains near 1228. as the ring becomes negative, the dtx transitions to ?32768. this repeats in cadence with the ring signal. to observe the ring signal on dtx, watch the msb of the data. the msb toggles at the same frequency as the ring signal independent of the ring detector mode. this method is adequate for determining the ring frequency. 5.19. ring validation ring validation prevents false triggering of a ring detection by validating the ring parameters. invalid signals, such as a line-voltage change when a parallel handset goes off-hook, pulse dialing, or a high-voltage line test are ignored. ring validation can be enabled during normal operation and in low-power sleep mode when a valid external pclk signal is supplied. the ring validation circuit operates by calculating the time between alternating crossings of positive and negative ring thresholds to validate that the ring frequency is within tolerance. high and low frequency tolerances are programmable in the ras[5:0] and rmx[5:0] fields. the rcc[2:0] bits define how long the ring signal must be within tolerance. once the duration of the ring frequency is validated by the rcc bits, the circuitry stops checking for frequency tolerance and begins checking for the end of the ring signal, which is defined by a lack of additional threshold crossings for a period of time configured by the rto[3:0] bits. when the ring frequency is first validated, a timer defined by the rdly[2:0] bits is started. if the rdly[2:0] timer expires before the ring timeout, then the ring is validated and a va lid ring is indicated. if the ring timeout expires before the rdly[2:0] timer, a valid ring is not indicated. ring validation requires the following five parameters: ? timeout parameter to place a lower limit on the frequency of the ring signal (the ras[5:0] bits in register 24). the frequency is measured by calculating the time between crossings of positive and negative ring thresholds. ? minimum count to place an upper limit on the frequency (the rmx[5:0] bits in register 22). ? time interval over which the ring signal must be the correct frequency (the rcc[2:0] bits in register 23). ? timeout period that defines when the ring pulse has ended based on the most recent ring threshold crossing. ? delay period between when the ring signal is validated and when a valid ring signal is indicated to accommodate distinctive ringing. the rngv bit (register 24, bit 7) enables or disables the ring validation feature in both normal operating mode and low-power sleep mode. ring validation affects the behavior of the rdt status bit, the rdti interrupt, the int pin, and the rgdt pin.
si3050 + si3011 28 rev. 1.11 1. when ring validation is enabled, the status bit seen in the rdt read-only bit (r5.2), represents the detected envelope of the ring. the ring validation parameters are configurable so that this envelope may remain high throughout a distinctive-ring sequence. 2. the rdti interrupt fires when a validated ring occurs. if rdi is zero (default), the interrupt occurs on the rising edge of rdt. if rdi is set, the interrupt occurs on both rising and falling edges of rdt. 3. the int pin follows the rdti bit with configurable polarity. 4. the rgdt pin can be configured to follow the ringing signal envelope detected by the ring validation circuit by setting rfwe to 0. if rfwe is set to 1, the rgdt pin follows an unqualified ring detect one-shot signal initiated by a ring-threshold crossing and terminated by a fixed counter timeout of approximately 5 seconds. (this information is shown in register 18). 5.20. ringer impedance the ring detector in a typical daa is ac coupled to the line with a large 1 f, 250 v decoupling capacitor. the ring detector on the si3011 is resistively coupled to the line. this coupling produces a high ringer impedance to the line of approximately 20 m ?? to meet fcc and tbr21 specifications. 5.21. pulse dialing pulse dialing is accomplished by going off- and on-hook to generate make and break pulses. the nominal rate is 10 pulses per second. some countries have strict specifications for pulse fi delity including make and break times, make resistance , and rise and fall times. in a traditional, solid-state dc holding circuit, there are a number of issues in meeting these requirements. the si3050 dc holding circuit has active control of the on- and off-hook transients to maintain pulse dialing fidelity. to ensure proper operation of the daa during pulse dialing, disable the automatic resistor calibration that is performed each time the daa enters the off-hook state by setting the rcald bit (register 25, bit 5). 5.22. receive overload detection the voice daa chipset is capable of monitoring and reporting receive overload co nditions on the line. billing tones, parallel phone off-hook events, polarity reversals and other disturbances on the line may trigger multiple levels of overload detection as described below. transient events less than 1.1 v pk on the line are filtered out by the low-pass digital filter on the si3050+si3011 chipset. the rov and rovi bits are set when the received signal is greater than 1.1 v pk . both bits will continue to indicate an overload condition until a zero is written to clear. the ovl mirrors the function of the rov and rovi bits but it automatically clears after the overload condition has been removed. when the ovl bit returns to 0, the daa initiates an auto-calibration sequence that must complete before data can be transmitted. an external interrupt can optionally be triggered by the rovi bit by setting the rovm and inte bits. certain events such as billin g tones can be sufficiently large to disrupt the line-derived power supply of the voice daa line side device. to ensure that the device maintains the off-hook line state during these events, the bte bit should be set. if such an event occurs while the bte bit is set, the btd and btdi bits will be asserted. a zero must be written to the bte bit to clear the btd and btdi bits. an external interrupt can optionally be triggered by the btdi bit by setting the btdm and inte bits. in the event that a line disturbance causes the loop current to collapse below the minimum required operating current of the voice daa, the dod and dodi bits will be set. an external interrupt can optionally be triggered by the dodi bit by setting the dodm and inte bits. 5.23. billing tone filter (optional) optionally, a billing tone filt er may be in serted between the line and the voice daa to minimize disruptions caused by large billing tone s. the notch filter design requires two notches, one at 12 khz and one at 16 khz. because these components are expensive and few countries utilize billing tones, th is filter is typically placed in an external dongle or added as a population option. figure 23 shows a billing tone filter example. table 16 gives the component values. l1 must carry the entire loop current. the series resistance of the inductors is important to achieve a narrow and deep notch. this design has more than 25 db of attenuation at both 12 khz and 16 khz.
si3050 + si3011 rev. 1.11 29 figure 23. billing tone filter the billing tone filt er affects the daa?s ac termination and return loss. 5.24. on-hook line monitor the on-hook line monitor mode allows the si3050 to receive line activity when in an on-hook state. this mode is typically used to detect caller id data (see ?5.25.caller id?) and is enabled by setting the onhm bit (register 5, bit 3). caller id data can be gained up or attenuated using the receive gain control bits in registers 39 and 41. 5.25. caller id the si3050 can pass caller id data from the phone line to a caller id decoder connected to the daa. 5.25.1. type i caller id type i caller id sends the cid data when the phone is on-hook. in systems where the caller id data is passed on the phone line between the first an d second rings, utilize the following method to capture the caller id data: 1. after identifying a ring signal using one of the methods described in "5.18. ring detection" on page 26, determine when the first ring is complete. 2. assert the onhm bit (register 5, bit 3) to enable caller id data detection. the caller id data is passed across the rng 1/2 pins and presented to the host via the dtx pin. 3. clear the onhm bit after the caller id data is received. in systems where the caller id data is preceded by a line polarity (battery) reversal, use the following method to capture the caller id data: 1. enable full wave rectifie d ring detection (rfwe, register 18, bit 1). 2. monitor the rdtp and rdtn register bits or the poli bit to identify if a polarity reversal or a ring signal has occurred. a polarity reversal trips either the rdtp or rdtn ring detection bits, therefore the full-wave ring detector must be used to distinguish a polarity reversal from a ring. the lowest specified ring frequency is 15 hz; so, if a battery reversal occurs, the dsp should wait a minimum of 40 ms to verify that the event is a battery reversal and not a ring signal. this time is greater than half the period of the longest ring signal . if another edge is detected during this 40 ms pause, th is event is characterized as a ring signal and not a battery reversal. 3. assert the onhm bit (register 5, bit 3) to enable caller id data detection. the caller id data is passed across the rng 1/2 pins and presented to the host via the dtx pin. 4. clear the onhm bit after the caller id data is received. 5.25.2. type ii caller id type ii caller id sends the cid data while the phone is off-hook. this mode is often referred to as caller id/ call waiting (cid/cw). to receive the cid data when off-hook, use the following procedure (also see figure 24): 1. the caller alert signal (cas) tone is sent from the central office (co) and is di gitized along with the line data. the host processor detects the presence of this tone. 2. the daa must check if there is another parallel device on the same line, which is accomplished by briefly going on-hook, measuring the line voltage, and returning to an off-hook state. a. set the cald bit (register 17, bit 5) to disable the calibration that automatically occurs when going off-hook. b. set the rcald bit (register 25, bit 5) to disable the resistor calibration th at automatically occurs when going off-hook c. set the foh[1:0] bits (register 31 bits 6:5) to 11 table 16. component values?optional billing tone filters component value c1,c2 0.027 f, 50 v, 10% c3 0.01 f, 250 v, 10% l1 3.3 mh, >120 ma, <10 ? , 10% l2 10 mh, >40 ma, <10 ? , 10% l2 c3 ring tip from line to daa c1 c2 l1
si3050 + si3011 30 rev. 1.11 to reduce the time period for the off-hook counter to 8 ms allowing compliance to the type ii cid timing requirements. d. clear the oh bit (register 5, bit 0). this puts the daa into an on-hook state. the rxm bit (register 15, bit 3) also can be set to mute the receive path. e. read the lvs bits to determine the state of the line. if the lvs bits read the typical on-hook line voltage, then there are no parallel devices active on the line, and cid data reception can be continued. if the lvs bits read well below the typical on-hook line voltage, then there are one or more devices present and active on the same line that are not compliant with type ii cid. do not continue cid data reception. f. set the oh bit to return to an off-hook state. immediately after returning to an off-hook state, the off-hook counter must be allowed to expire. this allows the line volt age to settle before transmitting or receiving data. after 8 ms normal data transmission and reception can begin. if a non-compliant parallel device is present, then a reply tone is not sent by the host tone generator and the co does not send the cid data. if all devices on the line are type ii cid compliant, then the host must mute its upstream data output to avoid the propagation of its reply tone and the subsequent cid data. when muting its upstream data output, the host processor should return an acknowledgement (ack) tone to the co requesting transmission of cid data. 3. the co then responds with cid data after receiving the cid data, the host processor unmutes the upstream data output and continues with normal operation. 4. the muting of the upstream data path by the host processor mutes the handset in a telephone application so the user cannot hear the acknowledgement tone and cid data being sent. 5. the cald and the rcald bits can be cleared to re-enable the automatic calibrations when going off-hook. the foh[1:0] bits also can be programmed to 01 to restore the default off-hook counter time. because of the nature of the low-power adc, the data presented on dtx can have up to a 10% dc offset. the caller id decoder must either use a high-pass or a band-pass filter to accurately retrieve the caller id data. figure 24. implementing type ii caller id on the si3050+si3011 notes: 1. the off-hook counter and calibrations prevent transmission or reception of data for 402.75 ms (default) for the line voltage to settle. 2. the caller alert signal (cas) tone transmits from the co to signal an incoming call. 3. the device is taken on-hook to read the line voltage in the l vs bits to detect parallel handsets. in this mode, no data is transmitted on the dtx pin. 4. when the device returns off-hook, the normal off-hook counter is reduced to 8 ms. if the cald and rcald bits are set, then the automatic calibrations are not performed. 5. after allowing the off-hook counter to expire (8 ms), normal transmission and reception can continue. if cid data reception is required, send the appropriate signal to the co at this time. line foh[1] bit rcald bit cald bit 1 234 5 oh bit foh[0] bit on-hook off-h ook c ounter and c alibration (402.75 ms nominally) off -hook ca s tone rec eiv ed on-hook off-hook counter (8 ms) off -hook a ck
si3050 + si3011 rev. 1.11 31 5.26. overload detection the si3050 can be programmed to detect an overload condition that exceeds the normal operating power range of the daa circuit. to use the overload detection feature, the following steps should be followed: 1. set the oh bit (register 5, bit 0) to go off-hook, and wait 25 ms to allow line transients to settle. 2. enable overload detection by then setting the ope bit (register 17, bit 3). if the daa senses an overload situation it automatically presents an 800 ? impedance to the line to reduce the hookswitch current. at this time, the daa also sets the opd bit (register 19, bit 0) to indicate that an overload condition exists. the line cu rrent detector within the daa has a threshold that is dependent on the ilim bit (register 26). when ilim = 0, the overload detection threshold equals 160 ma. when ilim = 1, the overload detection threshold equals 60 ma. the ope bit should always be cleared before going off-hook. 5.27. gain control the si3050 supports multiple levels of gain and attenuation for the transmit and receive paths. the txg2 and rxg2 bits (registers 38?39) enable gain or attenuation in 1 db increments for the transmit and receive paths (up to 12 db gain and 15 db attenuation). the tga2 and rga2 bits select either gain or attenuation. the txg3 and rxg3 bits (registers 40?41) enable gain or attenuation in 0.1 db increments up to 1.5 db for the transmit and receive paths. the tga3 and rga3 bits select either gain or attenuation. the transmit and receive paths can be individually muted with the txm and rxm bits (register 15). the signal flow through the si3050 and the si3011 is shown in figures 25?26. figure 25. si3011 signal flow diagram figure 26. si3050 signal flow diagram to si3050 adc dac link analog hybrid act tx co 0.6 hz hpf digital hybrid iire digital filter txg2 to si3011 link txg3 txa3 drx dtx 1 db gain steps 0.1 db gain/att steps txa2 1 db attenuation steps rxa2 1 db attenuation steps digital iire filter rxg3 0.1 db gain/att steps rxa3 1 db gain steps rxg2 selectable 200 hz hpf
si3050 + si3011 32 rev. 1.11 5.28. transhybrid balance the si3050 contains an on-c hip analog hybrid that performs the 2- to 4-wire conversion and near-end echo cancellation. this hybrid circuit is adjusted for each ac termination setting selected to achieve a minimum transhybrid balance of 20 db when the line impedance matches the impedance set by acim. the si3050 also offers a digital hybrid stage for additional near-end echo cancellation. for each ac termination setting, the eight programmable hybrid registers (registers 45?52) can be programmed with coefficients to increase cancellation of real-world line impedances. this digital filter can produce 10 db or greater of near-end echo cancellation in addition to the trans-hybrid loss from the analog hybrid circuitry. coefficients are 2s complement, where unity is represented as binary 0100 0000b, the maximum value as binary 0111 1111b, and the minimum value as binary 1000 000b. see an84 for a more detailed description of the digital hybrid and how to use it. 5.29. filter selection the si3050 supports additional filter selections for the receive and transmit signals as defined in tables 10 and 11. the iire bit (register 16, bit 4) selects between the iir and fir filters. the iir filter provides a shorter, but non-linear, group delay alternative to the default fir filter, and only operates with an 8 khz sample rate. the filt bit (register 31, bit 1) selects a ?3 db low frequency pole of 5 hz when cleared and a ?3 db low frequency pole of 200 hz (per eia/tia 464) when set. the filt bit affects the receive path only. 5.30. clock generation the si3050 generates the necessary internal clock frequencies from the pclk input. pclk must be synchronous to the 8 khz fsync clock and run at one of the following rates: 256khz, 512khz, 768khz, 1.024 mhz, 1.53 mhz, 2.048 mhz, 4.09 mhz, or 8.192 mhz. the ratio of the pclk rate to the fsync rate is determin ed internally by the daa and is transferred into internal registers after a reset. these internal registers are not accessible through register reads or writes. figure 27 shows the operation of the si3050 clock circuitry. the pll clock synthesizer settles quickly after powerup. however, the settling time depends on the pclk frequency and it can be approximately predicted by the following equation: t settle =64/f pclk for all valid pclk frequencies listed above, the default line sample rate is 8 khz. this sample rate can be increased to 16 khz by setting the hssm bit (register 7, bit 3). regard less of the sample rate frequency, the serial data communication rate of the pcm and gci highways remains 8 khz. when the 16 khz sample rate is selected, additional timeslots in the pcm or gci highway are used to transfer the additional data. 5.31. communication interface mode selection the si3050 supports two communication interface protocols: ? pcm/spi mode where data and control information transmission/reception occurs across separate buses (pcm highway for data, and spi port for control). ? gci mode where data and control information is multiplexed and transmission/reception occurs across the gci highway bus. a pin-strapping method (specifically, the state of sclk on power-up [reset]) is used to select between the two communication interface protocols. tables 16 and 17 specify how to select a communication mode, and how the various pins are used in each mode. when operating in pcm/spi mode, the gci control register should not be written (i.e., register 42 must each remain set at 0000_0000 when using the pcm/ spi highway mode). similarly, when operating in gci highway mode the pcm registers should not be written (i.e., registers 33?37 must remain set to 0000_0000 when using the gci highway mode).
si3050 + si3011 rev. 1.11 33 figure 27. pll clock synthesizer table 17. pcm or gci highway mode selection sclk sdi mode selected 1 x pcm mode 0 0 gci mode, b2 channel used 0 1 gci mode, b1 channel used note: values shown are the states of the pins at the rising edge of reset. pfd vco ? 2 16.384 mhz div m pclk internal pll register ? 2 ? n
si3050 + si3011 34 rev. 1.11 5.32. pcm highway the si3050 contains a flexible programmable interface for the transmission and reception of digital pcm samples. pcm data transfer is controlled via the pclk and fsync inputs, the pcm transmit and receive start count registers (registers 34?37), and the pcm mode select register (register 33). the interface can be configured to support from 4 to 128 8-bit timeslots in each frame, which corresponds to pclk frequencies of 256 khz to 8.192 mhz in power of 2 increments. time slot assignment and data delay from fsync edge are handled via the txs and rxs registers. these 10-bit values are programmed with the number of pclk cycles following the rising edge of fsync until the data transfer begins. because the si3050 looks for the rising edge of fsync, both long and short fsync pulse widths can be accommodated. a value of 0 in the pcm transmit and receive start count registers signifies that the msb of the data should occur in the same cycle as the rising edge of fsync. by setting the correct starting point of the data, the si3050 can operate with buses having multiple devices requiring different time slots. the dtx pin is high impedance except during transmission of an 8-bit pcm sample. dtx returns to high impedance either on the negative edge of pclk during the lsb or on the positive edge of pclk following the lsb. this behavior is based on the setting of the tri bit in the pcm mode select register. tristating on the negative edge allows the transmission of data by multiple sources in adjacent timeslots without the risk of driver contention. in addition to 8-bit data modes, a 16-bit linear mode is also provided. this mode can be activated via the pcmf bits in the pcm mode select register. double-clocked timing also is supported in which the duration of a data bit is two pclk cycles. this mode is activated via the phcf bit in the pcm mode select register. setting the txs or rxs registers greater than t he number of pclk cycles in a sample period stops data transmission or reception. figures 28?31 illustrate the usage of the pcm highway interface to adapt to common pcm standards. table 18. pin functionality in pcm or gci highway mode pin name pcm mode gci mode sdi_thru spi data throughput pin for daisy chaining operation (connects to the sdi pin of the subsequent device in the daisy chain) sub-frame selector, bit 2 sclk spi clock input pcm/gci mode selector sdi spi serial data input b1/b2 channel selector sdo spi serial data output sub-frame selector, bit 1 cs spi chip select sub-frame selector, bit 0 fsync pcm frame sync input gci frame sync input pclk pcm input clock gci input clock dtx pcm data transmit gci data transmit drx pcm data receive gci data receive note: this table denotes pin functionality after th e rising edge of reset and mode selection.
si3050 + si3011 rev. 1.11 35 figure 28. pcm highway transmission, short fsync, single clock cycle delayed transmission (txs = rxs = 0, phcf = 0, tri = 1) figure 29. pcm highway transmission, long fsync (txs = rxs = 0, phcf = 0, tri = 1) 01 7 6 5 4 3 2 16 15 14 13 12 11 10 9 818 17 msb lsb msb lsb hi-z hi-z pclk fsync pclk_cnt drx dtx 01 7 6 5 4 3 2 16 15 14 13 12 11 10 9 818 17 msb lsb msb lsb hi-z hi-z pclk fsync pclk_cnt drx dtx
si3050 + si3011 36 rev. 1.11 figure 30. pcm highway transmission, long fsync, delayed data transfer (txs = rxs = 10, phcf = 0, tri = 1) figure 31. pcm highway double clocked transmission, short fsync (txs = rxs = 0, phcf = 1, tri = 1) 01 7 6 5 4 3 2 16 15 14 13 12 11 10 9 818 17 msb lsb msb lsb hi-z hi-z pclk fsync pclk_cnt drx dtx 01 7 6 5 4 3 2 16 15 14 13 12 11 10 9 818 17 msb lsb msb lsb hi-z hi-z pclk fsync pclk_cnt drx dtx
si3050 + si3011 rev. 1.11 37 5.33. companding in pcm mode the si3050 supports both -law and a-law companding formats in addition to 16-bit linear data. the 8-bit companding schemes follow a segmented curve formatted as a sign bit, three chord bits, and four step bits. -law is commonly used in north america and japan, while a-law is primarily used in europe. data format is selected via the pcmf bits (register 33). table 19 on page 38 and table 20 on page 39 define the -law and a-law encoding formats. if linear mode is used the resulting 16-bit data is transmitted in two consecutive 8-bit pcm highway timeslots as shown in figure 32. 5.34. 16 khz sampling operation in pcm mode the si3050 can be configured to support a 16 khz sampling rate and transmit the data on an 8 khz pcm or gci highway bus. by setting the hssm bit (register 7, bit 3) to 1, the daa changes its sampling rate, fs, to 16 khz if it was originally configured for an 8 khz sampling rate. if - law or a-law companding is used, the resulting 8-bit samples are transmitted in two consecutive 8-bit pcm highway timeslots. if linear mode is used, the resulting 16-bit samples are transmitted in four consecutive 8-bit pcm highway timeslots as shown in figure 33. figure 32. pcm highway transmission, single clock cycle, 16-bit linear mode (txs = rxs = 0, phcf = 0, tri = 1, pcmf = 11) figure 33. pcm highway transmission, single clock cycle, 16-bit linear mode (txs = rxs = 0, phcf = 0, tri = 1, pcmf = 11, hssm = 1) 01 7 6 5 4 3 2 16 15 14 13 12 11 10 9 818 17 msb lsb msb lsb hi-z hi-z pclk fsync pclk_cnt drx dtx msb msb hi-z lsb lsb hi-z sample 1 sample 2 01 7 6 5 4 3 216 15 14 13 12 11 10 9 818 17 19 20 26 25 24 23 22 21 35 34 33 32 31 30 29 28 27 36 37 pclk fsync pclk_cnt drx dtx
si3050 + si3011 38 rev. 1.11 table 19. -law encode-decode characteristics 1,2 segment number #intervals x interval size value at segment endpoints digital code decode level 8 16 x 256 8159 . . . 4319 4063 10000000b 1000 1111b 8031 4191 7 16 x 128 . . . 2143 2015 100 11111b 2079 6 16 x 64 . . . 1055 991 1010 1111b 1023 5 16 x 32 . . . 511 479 10111111b 495 4 16 x 16 . . . 239 223 11001111b 231 3 16 x 8 . . . 103 95 11011111b 99 2 16 x 4 . . . 35 31 11101111b 33 1 15 x 2 __________________ 1 x 1 . . . 3 1 0 11111110b 11111111b 2 0 notes: 1. characteristics are symmetrical about analog 0 with sign bit = 1 for negative analog values. 2. digital code includes inversion of both sign and magnitude bits.
si3050 + si3011 rev. 1.11 39 table 20. a-law encode-decode characteristics 1,2 segment number #intervals x interval size value at segment endpoints digital code decode level 7 16 x 128 4096 3968 . . 2143 2015 10101010b 10100101b 4032 2112 616 x 64 . . . 1055 991 10110101b 1056 516 x 32 . . . 511 479 10000101b 528 416 x 16 . . . 239 223 10010101b 264 316 x 8 . . . 103 95 11100101b 132 216 x 4 . . . 35 31 11110101b 66 132 x 2 . . . 2 0 11010101b 1 notes: 1. characteristics are symmetrical about analog 0 with sign bit = 1 for negative analog values. 2. digital code includes inversion of all even numbered bits.
si3050 + si3011 40 rev. 1.11 5.35. spi control interface the control interface to the si3050 is a 4-wire interface modeled on commonly available micro-controller and serial peripheral devices. the interface consists of four pins: clock (sclk), chip select (cs ), serial data input (sdi), and serial data output (sdo). in addition, the si3050 includes a serial data through output pin (sdithru) to support daisy chain operation of up to 16 devices. the device can operate with 8-bit and 16-bit spi controllers. each spi operation consists of a control byte, an address byte (of which only the six lsbs are used internally), and either one or two data bytes depending on the width of the controller. bytes are transmitted msb first. there are a number of variations of usage on this four-wire interface as follows: ? continuous clocking. during continuous clocking, assertion of the cs pin controls the data transfers. the cs pin must be asserted before the falling edge of sclk on which the first bit of data is expected during a read cycle, and must remain low for the duration of the 8-bit transfer (command/address or data), going high after the last rising edge of sclk after the transfer. ? clock only during transfer. the clock is active during the actual byte transfers only. each byte transfer consists of eight clock cycles in a return to 1 format. ? sdi/sdo wired operation. independent of the clocking options described, the sdi and sdo pins can be treated as two separate lines or wired together if the master can tri-state its output during the data byte transfer of a read operation. the spi state machine resets when the cs pin is asserted during an operation on an sclk cycle that is not a multiple of eight. this provides a mechanism for the controller to force the state machine to a known state in the case where the controller and the device are not synchronized. the control byte has the following structure and is presented on the sdi pin msb first. the bits are defined as follows: 7654 3 210 brct r/w 1 0 cid[0] cid[1] cid[2] cid[3] 7brct indicates a broadcast operation that is intended for all devices in the daisy chain. this is only valid for write operations as it causes contention on the sdo pin during a read. 6r/w read/write bit. 1 = read operation. 0 = write operation. 5 1 this bit must be 1 at all times. 4 0 this bit must be 0 at all times. 3:0 cid[0:3] this field indicates the channel that is targeted by the operation. the 4-bit channel value is pro- vided lsb first. the devices reside on the daisy c hain such that device 0 is nearest to the con- troller and device 15 is furthest away in the sdi/sdithru chain. see figure 34. as the cid information propagates down the dais y chain, each channel decrements the cid by 1. the device that receives a value of 0 in th e cid field responds to the spi transaction. see figure 35. if a broadcast to all devices connect ed to the chain is requested, the cid do not decrement. in this case, the same 8- or 16-bit data is presented to all channels regardless of the cid values.
si3050 + si3011 rev. 1.11 41 figure 34. spi daisy chain control architecture figure 35. sample spi control byte to access channel 0 cpu sdo cs sdi cs sdi sdithru sdo channel 0 si3050 #1 cs sdi sdithru sdo channel 1 si3050 #2 cs sdi sdithru sdo channel 15 si3050 #16 sclk sclk sclk sclk spi control byte brct r/w 1 0 cid[0] cid[1] cid[2] cid[3] 0 0 or 1 1 0 0 0 0 0 0 0 or 1 1 0 1 0 0 0 0 0 or 1 1 0 0 1 0 0 0 0 or 1 1 0 1 1 0 0 0 0 or 1 1 0 0 1 1 1 0 0 or 1 1 0 1 1 1 1 sdi0 sdi1 sdi2 sdi3 sdi14 sdi15
si3050 + si3011 42 rev. 1.11 figure 36. sample spi control byte for broadcast mode (write only) in figure 35 the cid field is 0. as this field is decremen ted in lsb to msb order, the value decrements for each sdi down the line. the brct and r/w bits remain unchanged as the control word passes through the entire chain. a unique cid is presented to each device, and the device re ceiving a cid value of 0 is the target of the operation (channel 0 in this case). figure 36 illu strates that in br oadcast mode, all bits pass through the chain without permutation. figure 37. write operation via an 8-bit spi port figure 38. read operation via an 8-bit spi port figure 37 and figure 38 illust rate write and read operations via an 8-bit spi controller. ea ch of these operations are performed as a 3-byte transfer. the cs pin is asserted between each byte. the cs pin must be asserted before the first falling edge of sclk after the data byte to indica te to the state machine that only one byte should be transferred. the state of the sdi pin is ignored during the data byte of a read operation. figure 39. write operation via a 16-bit spi port 1 0 1 0 x x x x sdi0-15 control address data [7:0] csb sclk sdi sdo hi-z control address xxxxxxxxxxxx csb sclk sdi sdo data [7:0] x x x x x x x x csb sclk sdi sdo control address data [7:0] hi - z
si3050 + si3011 rev. 1.11 43 figure 40. read operation via a 16-bit spi port figures 39 and 40 illustrate write and read operations via a 16-bit spi cont roller. these operations require a 4-byte transfer arranged as two 16-bit words. the cs pin does not go high when the eighth bit of data is received, which indicates to the spi state machine that eight more sclk pulses follow to complete the operation. in the case of a write operation, the last eight bits are ignored. in a read operation, the 8-bit data value is repeated so that the data may be captured during the last half of a data tr ansfer if required by the controller. the si3050 autodetects the spi mode (16-bit or 8-bit mode). x x x x x x x x csb sclk sdi sdo data [7:0] control address x x x x x x x x data [7:0] same byte repeated twice.
si3050 + si3011 44 rev. 1.11 5.36. gci highway the si3050 contains an alternate communication interface to the spi and pcm highway control and data interface. the general circ uit interface (gci) can be used for the transmission and reception of control and data information onto a gci highway bus. the pcm and gci highways are 4-wire interfaces and share the same pins. the spi control interface is not used as a communication interface in the gci highway mode, but rather as hardwired channel selector pins. when gci mode is selected, the sub-frame selection pins must be tied to the correct state to select one of eight sub-frame timeslots in the gci frame (table 21). these pins must remain in this state when the si3050 is operating. selecting a particular subframe automatically causes that individual si3050 to transmit and receive on the appropriate sub-frame in the gci frame, which is initiated by an fsync pulse. no more register settings are needed to select which sub-frame a device uses, and the sub-frame for a particular device cannot be changed when in operation. only one si3050 daa can be assigned per sub-frame, which allows a total of eight daas to be connected to the same gci highway bus. gci mode supports a 1x and a 2x pclk rate as shown in figures 5 and 6 on pages 13 and 14, respectively. the pclk rate is autodetected and no internal register settings are needed to support either 1x or 2x pclk mode. the gci highway requires either a 2.048 or 4.096 mhz clock frequency on the pclk pin, and an 8 khz frame sync input on the fsync pin. the overall unit of data used to communicate on the gci highway is a frame, which is 125 s in length. ea ch frame is in itiated by a pulse on the fsync pin and the rising edge signifies the beginning of the next frame. in 2x pclk mode, there are twice as many pclk cycles during each 125 s frame versus 1x pclk mode. each frame consists of eight fixed timeslot sub-frames that are assigned using the sub-frame select pins as described in table 18 on page 34 (sdi_thru, sdo, and cs ). within each sub-frame are four channels (bytes) of data, including the two voice data channels (b1 and b2), one monitor channel (m) for initialization and setup of the device, and one signaling and control channel (sc) for communicating status of the device and for initiating commands. within the sc channel are six command/indicate (c/i) bits and two handshaking bits (mr and mx). the c/i bits are used for status and command communication, whereas the handshaking bits monitor receive (mr) and monitor transmit (mx) are used for data exchanges in the monitor channel. figure 41 illustrates the contents of a gci highway frame. 5.37. companding in gci mode the si3050 supports -law and a-law companding formats in addition to 8-bit or 16-bit linear data. the 8-bit companding schemes are described in "5.33. companding in pcm mode" on page 37 and are shown in table 19 and table 20. if 16-bit linear mode is used, the resulting 16-bit samples are transmitted in both the b1 and b2 channels of a single subframe. for proper operation, select all si3050 daas to use the b1 channel with only one daa per subframe. 5.38. 16 khz sampling operation in gci mode the si3050 can be configured to support a 16 khz sampling rate (as described in "5.3 4. 16 khz sampling operation in pcm mode" on page 37) and transmit the data on an 8 khz gci highway bus. if 8-bit samples are used with a 16 khz sample rate, the samples are transmitted in both the b1 and b2 channels of a single subframe. if 16-bit linear mo de is used, the resulting 16-bit samples are transmitted in both the b1 and b2 channels of two consecutive subframes. in this case, assign one daa per two subframes. 5.39. monitor channel the monitor channel is used for initialization and setup of the si3050. it also can be used for general communication with the si3050 by allowing read and write access to the si3050?s registers. use of the monitor channel requires manipulation of the mr and mx handshaking bits, located in bits 1 and 0 of the sc channel described below. for purposes of this specification, ?downstream? is identified to be the data sent by a host to the si3050. ?upstream? is identified to be the data sent by the si3050 to a host. table 21. gci mode sub-frame selection sdi_thru sdo cs gci subframe 0 selected (voice channels 1?2) 111 gci subframe 1 selected (voice channels 3?4) 110 gci subframe 2 selected (voice channels 5?6) 101 gci subframe 3 selected (voice channels 7?8) 100 gci subframe 4 selected (voice channels 9?10) 011 gci subframe 5 selected (voice channels 11?12) 010 gci subframe 6 selected (voice channels 13?14) 001 gci subframe 7 selected (voice channels 15?16) 000
si3050 + si3011 rev. 1.11 45 figure 41 illustrates th e monitor channel communicati on protocol. for successful communication with the si3050, the transmitter should anticipate the falling edge of the receiver?s ac knowledgement. this also maximizes communication speed. because of the handshaking prot ocol required for successful communication, the data transfer rate using the monitor channel is less than 8 kbytes/second. figure 41. time-multiplexed gci highway frame structure figure 42. monitor handshake timing fsync 125 ? s channel 01 2611 sc channel sub-frame sf1 sf2 sf3 sf4 sf5 sf6 sf7 sf0 mr mx c/i m b2 b1 88 8 transmitter receiver 1st byte 2nd byte 3rd byte mx mx mr ack 1st byte ack 2nd byte ack 3rd byte 125 ? s mr
si3050 + si3011 46 rev. 1.11 the idle state is achieved by the mx and mr bits being held inactive (signal is hi gh) for two or more frames. when a transmission is initiated by a host device, an active state (signal is low) is present on the downstream mx bit. this signals to the si3050 that a transmission has begun on the monitor channel and the si3050 should begin accepting data from host device. the si3050, after reading the data on the monitor channel, acknowledges the initial transmission by placing the upstream mr bit in an active state. the data is received and the upstream mr becomes active in the frame immediately following the downstream mx becoming active. the upstream mr then remains active until either the next byte is received or an end of message is detected. the end of message is signaled by the downstream mx being held inactive for two or more consecutive frames. receipt of initial data is signaled by the upstream mr bit?s transitioning from an inactive to an active state. upon receiving acknowledgement from the si3050 that the initial data is received, the host device places the downstream mx bit in the inactive state for one frame and then either transmit another byte by placing the downstream mx bit in an active state again, or signal an end of message by leaving the downstream mx bit inactive for a second frame. when the host is performi ng a write command, the host only manipulates the downstream mx bit, and the si3050 only manipulates the upstream mr bit. if a read command is performed, the host initially manipulates the downstream mx bit to communicate the command, but then manipulates the downstream mr bit in response to the si3050 responding with the requested data. similarly, the si3050 initially manipulates its upstream mr bit to receive the read command, and then manipulates its upstream mx bit to respond with the requested data. if the host is transmitting data, the si3050 always transmits a $ff value on its monitor data byte. while the si3050 is transmitting data, the host should always transmit a $ff value on its monitor byte. if the si3050 is transmitting data and detects a value other than a $ff on the downstream monitor byte, the si3050 signals an abort. for read and write commands, an initial address must be specified. the si3050 responds to a read or a write command at this address, and then subsequently increment this address after every register access. in this manner, multiple consecutive registers can be read or written in one transmission sequence. by correctly manipulating the mx and mr bits, a transmission sequence can continue from the beginning specified address until an invalid memory location is reached. to end a transmission sequence, the host processor must signal an end-of-message (eom) by placing the downstream mx and mr bits inactive for two consecutive frames. the transmission also can be stopped by the si3050 by signaling an abort. this is signaled by placing the upstream mr bit inactive for at least two consecutive cycles in response to the downstream mx bit going active. an abort is signaled by the si3050 for the following reasons: ? a read or write to an invalid memory address is attempted ? an invalid command sequence is received ? a data byte was not received for at least two consecutive frames ? a collision occurs on the monitor data bytes while the si3050 is transmitting data when the si3050 aborts because of an invalid command sequence, the state of the si3050 does not change. if a read or write to an invalid memory address is attempted, all previous reads or writes in that transmission sequence are valid up to the read or write to the invalid memory address. if an eom is detected before a valid command se quence is communicated, the si3050 returns to the idle state and remains unchanged. the data presented to the si3050 in the downstream monitor bits must be present for two consecutive frames to be considered valid data. the si3050 checks to ensure it receives the same data in two consecutive frames. if not, it does not acknowledge receipt of the data byte and waits until it does receive two consecutive identical data bytes before acknowledging to the transmitter that it received the data. if the transmitter attempts to signal transmission of a subsequent data byte by placing the downstream mx bit in an inactive state while the si3050 is still waiting to receive a valid data byte transmission of two consecutive identical data bytes, the si3050 signals an abort and ends the transmission. figure 43 shows a state diagram for the receiver monitor channel for the si3050. figure 44 on page 48 shows a state diagram for the transmitter monitor channel for the si3050.
si3050 + si3011 rev. 1.11 47 figure 43. si3050 monitor receiver state diagram mx mx mx mx mx mx mx mx mx x ll mx x ll mx x ll initial state any state mx x ll abt mr: mr bit calculated and transmitted on dtx line. mx: mx bit received data downstream (drx line). ll: last look of monitor byte received on drx line. abt: abort indication to internal source. mx nth byte received mr = 1 new byte mr = 1 byte valid mr = 0 1st byte received mr = 0 abort mr = 1 wait for ll mr = 0 wait for ll mr = 0 idle mr = 1 mx x ll mx x ll
si3050 + si3011 48 rev. 1.11 figure 44. si3050 monitor transmitter state diagram initial state mr: mr bit received on drx line. mx: mx bit calculated and expected on dtx line. mxr: mx bit s am pled on dtx line. cls: collision within the monitor data byte on dtx line. rqt: request for transmission from internal source. abt: abort request/indication. mr mr cls/ abt mxr mr x mxr mr x mxr mr x mxr mr mr x r q t mr x r q t mr x r q t mr x r q t mr x r q t mr any state eom mx = 1 1st byte mx = 0 wait mx = 1 ab o rt mx = 1 nth byte ack mx = 1 wait for ack mx = 0 idle mr = 1
si3050 + si3011 rev. 1.11 49 monitor data downstream $ff $ff $91 $91 $81 $81 $10 $10 $ff $ff $ff $ff $ff $ff $ff $ff $ff 125 ? s 1 frame mx downstream bit mr downstream bit monitor data upstream $ff $ff $ff $ff $ff $ff $ff $ff $ff $91 $91 contents of register $10 contents of register $10 contents of register $11 contents of register $11 contents of register $12 (ignored by host) $ff mx upstream bit mr upstream bit sends address before data eom acknowledge eom signalled = acknowledgement of data reception device address r/w register address device address figure 45. example read of registers $10 and $11 in subframe 0 of the si3050
si3050 + si3011 50 rev. 1.11 monitor data downstream $ff $ff $91 $91 $01 $01 $10 $10 data to be written to $10 data to be written to $10 data to be written to $11 data to be written to $11 $ff $ff 125 ? s 1 frame mx downstream bit mr downstream bit monitor data upstream $ff $ff $ff $ff $ff $ff $ff $ff $ff $ff $ff $ff $ff $ff mx upstream bit mr upstream bit eom acknowledge eom signalled = acknowledgement of data reception device address r/w register address figure 46. example write to registers $10 and $11 in subframe 0 of the si3050
si3050 + si3011 rev. 1.11 51 5.40. summary of monitor channel commands communication with the si3050 should be in the following format: byte 1: device address byte byte 2: command byte byte 3: register address byte bytes 4-n: data bytes bytes n+1, n+2: eom 5.41. device address byte the device address byte identifies which device connected to the gci highway receives the particular message. this address should be the first byte sent to the si3050 at the beginning of every transmission sequence. for read commands, the address sent to the si3050 is the first byte transmitted in response to the read command before register data is transmitted. this device address byte has the following structure: the lowest programmable bit, c, has a special function. this bit enables a register read or write, or enables a special channel identification command (cid). c = 1: normal command follows. c = 0: channel identification command. the cid is a special command to identify themselves by software. for this special command, the subsequent command byte transmitted by the host processor must be $00 (binary), and have no address or data bytes. the si3050 in turn responds with a fixed 2-byte identification code: upon sending the 2-byte identification code, the si3050 sends an eom (mr = mx = 1) for two consecutive frames. when a = 0, b must be 0 or the si3050 signals an abort due to an invalid command. in this mode, bit c is the only other programmable bit. a = 0: response to cid command from the device using channel b1 is placed in monitor data. a = 1: response to cid command from the device using channel b2 is placed in monitor data. when c = 1, bits a and b are channel enable bits. when these bits are set to 1, the individual corresponding channels receives the command in the next command byte. the channels whose corresponding bits are set to 0 ignores the subsequent command byte. a = 1: channel b1 receives the command. a = 0: channel b1 does not receive the command. b = 1: channel b2 receives the command. b = 0: channel b2 does not receive the command. 5.42. command byte the command byte has the following structure: the rw bit is a register read/write bit. rw = 0: a write is performed to the si3050?s register. rw = 1: a read is performed on the si3050?s register. the cmd[6:0] bits specif y the actual command to be performed. cmd[6:0] = 0000001: read or write a register on the si3050. cmd[6:0] = 0000010 ? 1111111: reserved. 5.43. register address byte the register address byte has the following structure: this byte contains the actual 8-bit address of the register to be read or written. 5.44. sc channel the sc channel consists of six c/i bits and two handshaking bits, mr and mx. one of these channels is contained in every 4-byte sub-frame and is transmitted every frame. the handshaking bits are described in the above monitor channel section. the definition of the six c/i bits depends on the direction the bits are being sent, either transmitted to the gci highway bus via the dtx pin or received from the gci highway bus via the drx pin. 100ab00c 100a0000 10111110 rw cmd[6:0] address[7:0]
si3050 + si3011 52 rev. 1.11 5.45. receive sc channel : these bits are defined as follows: cir6: reserved cir5: reserved cir4: onhm cir3: tgde cir2: rg cir1: oh data that is received must be consistent and match for at least two consecutive fram es to be considered valid. when a new command or status is communicated via the c/i bits, the data must be sent for at least two consecutive frames to be recognized by the si3050. the following steps describe the protocol of how c/i bits are stored, detected, and validated. this is illustrated in figure 47. 1. the current state of the c/i bits are stored in a primary re gister p. if the received c/ i bits are identical to this current state, no action is taken. 2. upon receipt of an sc channel with c/i bits that differ from the current state, these new c/i bits are immediately latched into a secondary register s. 3. the c/i bits in the sc channel received in the frame immediately after the sc channel just stored in s are compared with the c/i bits in the s register. a. if the c/i bits in these two channels are identical, then the c/i bits in the s register are loaded into the p register and are considered a valid change of c/i bits. the si3050 then re sponds accordingly to the changed c/i bits. b. if a set of c/i bits is latched into the s register and the subsequent set of c/i bits received does not match either the s or p registers, then the newly received set of c/i bits are latched into the s register. this continues to occur as long as the subsequent set of c/ i bits received differs from the c/i bits in the s and pregisters. c. if the c/i bits in the sc channel received immediatel y after the sc channel just stored in s do not match the c/i bits stored in s, but do match the c/i bits stored in p, then the single set of c/i bits stored in the s latch are invalidated, and the current state of the c/i bits in p remains unchanged. cir6 cir5 cir4 cir3 cir2 cir1 mr mx 76 5 4 3 21 0 c/i bits msb lsb
si3050 + si3011 rev. 1.11 53 figure 47. protocol for receiving c/i bits in the si3050 5.46. transmit sc channel the following diagram shows the definition of the tran smitted sc channel, which is transmitted msb first. these bits are defined as follows: cit6: reserved cit5: cvi cit4: dod cit3: int (represents the state of the int pin) cit2: battery reversal (represents the state of bit 7 of the lvs register) cit1: tgd receive new ci code store in s receive new c/i code = p? = p? = s? load c/i register with new c/i bits yes no yes yes no no p: c/i primary register contents s: c/i secondary register contents cit6 cit5 cit4 cit3 cit2 cit1 mr mx 76 5 4 3 21 0 c/i bits msb lsb
si3050 + si3011 54 rev. 1.11 6. control registers note: registers not listed here are reserved and must not be written. table 22. register summary register name bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 1 control 1 sr pwmm[1:0] pwme idl 2 control 2 inte intp wdten rdi hbe rxe 3 interrupt mask rdtm rovm fdtm btdm dodm lcsom tgdm polm 4 interrupt source rdti rovi fdti btdi dodi lcsoi tgdi poli 5 daa control 1 rdtn rdtp onhm rdt oh 6 daa control 2 pdl pdn 7 sample rate control hssm 8 reserved 9 reserved 10 daa control 3 ddl 11 system- and line-side device revision lsid[3:0] reva[3:0] 12 line-side device status fdt lcs[4:0] 13 line-side device revision 1 revb[3:0] 14 daa control 4 rpol 15 tx/rx gain control 1 txm rxm 16 international control 1 iire 17 international control 2 calz mcal cald ope bte rov btd 18 international control 3 rfwe 19 international control 4 ovl dod opd 20 call progress rx attenuation arm[7:0] 21 call progress tx attenuation atm[7:0] 22 ring validation control 1 rdly[1:0] rmx[5:0] 23 ring validation control 2 rdly[2] rto[3:0] rcc[2:0] 24 ring validation control 3 rngv ras[5:0] 25 resistor calibration rcals rcalm rcald rcal[3:0] 26 dc termination control 0 0 ilim dcr 27 reserved 28 loop current status lcs2[7:0] 29 line voltage status lvs[7:0] 30 ac termination control full2 acim 31 daa control 5 foh[1:0] 0 ohs2 0 filt lvfd 32 ground start control tgd tgde rg 33 pcm/spi mode select pcml pcme pcmf[1:0] 0 phcf tri 34 pcm transmit start count?low byte txs[7:0] 35 pcm transmit start count?high byte txs[1:0] 36 pcm receive start count?low byte rxs[7:0] 37 pcm receive start count?high byte rxs[1:0] 38 tx gain control 2 tga2 txg2[3:0] 39 rx gain control 2 rga2 rxg2[3:0] 40 tx gain control 3 tga3 txg3[3:0] 41 rx gain control 3 rga3 rxg3[3:0] 42 gci control gcif[1:0] b2d b1d 43 line current/voltage threshold interrupt cvt[7:0] 44 line current/voltage threshold interrupt control cvi cvs cvm cvp 45?52 programmable hybrid register 1?8 hyb1?8[7:0] 53?58 reserved 59 rx gain control 1 rg1 gce
si3050 + si3011 rev. 1.11 55 reset settings = 0000_0000 register 1. control 1 bit d7d6d5d4d3d2d1d0 name sr pwmm[1:0] pwme idl type r/w r/w r/w r/w bit name function 7sr software reset. 0 = enables the daa for normal operation. 1 = sets all registers to their reset value. note: bit automatically clears after being set. 6 reserved read returns zero. 5:4 pwmm[1:0] pulse width modulation mode. used to select the type of signal output on the call progress aout pin. 00 = pwm output is clocked at 16.384 mhz as a delta-sigma data stream. a local density of 1s and 0s tracks the combined transmit and receive signals. use this setting with the optional call progress circuit shown in figure 18 on page 19. 01 = balanced conventional pwm output signal ha s high and low portions of the modulated pulse that are centered on the 16 khz sample clock. 10 = conventional pwm output signal returns to logic 0 at regular 32 khz intervals and rises at a time in the 32 khz period proportional to its instantaneous amplitude. 11 = reserved. 3 pwme pulse width modulation enable. 0 = pulse width modulation mode disabled (aout). 1 = enable pulse width modulation mode for t he call progress analog output (aout). this mode sums the transmit and receive audio paths and presents this as a cmos digital-level output of pwm data. the circuit in figure 18 on page 19 should be used. 2 reserved read returns zero. 1idl isolation digital loopback. 0 = digital loopback across the isolation barrier is disabled. 1 = enables digital loopback mode across the isolation barrier. the line-side device must be enabled and off-hook prior to setting this mode. the data path includes the tx and rx filters. 0 reserved read returns zero.
si3050 + si3011 56 rev. 1.11 reset settings = 0000_0011 register 2. control 2 bit d7d6d5 d4 d3d2d1d0 name inte intp wdten rdi hbe rxe type r/w r/w r/w r/w r/w r/w bit name function 7inte interrupt pin enable. 0=the aout/int pin functions as an analog output for call progress monitoring purposes. 1=the aout/int pin functions as a hardware interrupt pin. 6intp interrupt polarity select. 0=the aout/int pin, when used in hardware interrupt mode, is active low. 1=the aout/int pin, when used in hardware interrupt mode, is active high. 5 reserved read returns zero. 4wdten watchdog timer enable. 0 = watchdog timer disabled. 1 = watchdog timer enabled. when set, this bit can be cleared only by a hardware reset. the watchdog timer monitors register access. if no register access occurs within a 4 s window, the daa is put into an on-hook state. a read or writ e of a daa register restarts the watchdog timer counter. if the watchdog timer ti mes out, the oh bit is cleared, placing the daa into an on-hook state. setting the oh bit places the daa back into an off-hook state. 3 reserved read returns zero. 2rdi ring detect interrupt mode. this bit operates in conjunction with the rdtm and rdti bits. this bit selects whether one or two interrupts are generated for every ring burst. 0 = an interrupt is generated at the beginning of every ring burst. 1 = an interrupt is generated at the beginning an d end of every ring burst. the interrupt at the beginning of the ring burst must be serviced (by writing 0 to the rdti bit) before the end of the ring burst in order for both interrupts to occur. 1hbe hybrid enable. 0 = disconnects hybrid in transmit path. 1 = connects hybrid in transmit path. 0rxe receive enable. 0 = receive path disabled. 1 = enables receive path.
si3050 + si3011 rev. 1.11 57 reset settings = 0000_0000 register 3. interrupt mask bit d7d6d5d4d3 d2 d1d0 name rdtm rovm fdtm btdm dodm lcsom tgdm polm type r/w r/w r/w r/w r/w r/w r/w r/w bit name function 7 rdtm ring detect mask. 0 = a ring signal does not cause an interrupt on the aout/int pin. 1 = a ring signal causes an interrupt on the aout/int pin. 6rovm receive overload mask. 0 = a receive overload does not cause an interrupt on the aout/int pin. 1 = a receive overload causes an interrupt on the aout/int pin. 5fdtm frame detect mask. 0 = the isocap losing frame lock does not cause an interrupt on the aout/int pin. 1 = the isocap losing frame lock causes an interrupt on the aout/int pin. 4btdm billing tone detect mask. 0 = a detected billing tone does not cause an in terrupt on the aout/int pin. 1 = a detected billing to ne causes an interr upt on the aout/int pin. 3dodm drop out detect mask. 0 = a line supply dropout does not cause an interrupt on the aout/int pin. 1 = a line supply dropout causes an interrupt on the aout/int pin. 2lcsom loop current sense overload mask. 0 = an interrupt does not occur when the lcs bits are all 1s. 1 = an interrupt occurs when the lcs bits are all 1s. 1tgdm tip ground detect mask. 0 = the tgd bit going active does not cause an interrupt on the aout/int pin. 1 = the tgd bit going active causes an interrupt on the aout/int pin. 0polm polarity reversal detect mask. this interrupt is generated from bit 7 of the lvs r egister. when this bit transitions, it indicates that the polarity of ti p and ring is switched. 0 = a polarity change on tip and ring does not cause an interrupt on the aout/int pin. 1 = a polarity change on tip and ring causes an interrupt on the aout/int pin.
si3050 + si3011 58 rev. 1.11 reset settings = 0000_0000 register 4. interrupt source bit d7d6d5d4d3d2d1d0 name rdti rovi fdti btdi dodi lcsoi tgdi poli type r/wr/wr/wr/wr/wr/wr/wr/w bit name function 7 rdti ring detect interrupt. 0 = a ring signal is not occurring. 1 = a ring signal is detected. if the rdtm bit (register 3) and inte bit (register 2) are set, a hardware interrupt oc curs on the aout/int pin. this bit must be written to a 0 to be cleared. the rdi bit (register 2) determines if this bit is set only at the beginning of a ring pulse, or at the both the beginning and end of a ring pulse. this bit should be cleared after clearing the pdl bit (register 6) as powering up the line-side device can cause this interrupt to be trig- gered. 6rovi receive overload interrupt. 0 = normal operation. 1 = an excessive input level on the receive pin is detected. if the rovm bit (register 3) and inte bit (register 2) are set, a hardware interrupt occurs on the aout/int pin. this bit must be written to 0 to clear it. this bit is identical in function to the rov bit (register 17) and clear- ing this bit also clears the rov bit. 5 fdti frame detect interrupt. 0 = frame detect is established on the isocap link. 1 = this bit is set when the isocap link does no t have frame lock. if the fdtm bit (register 3) and inte bit (register 2) are set, a hardware interrupt occurs on the aout/int pin. when set, this bit must be written to 0 to be cleared. 4btdi billing tone detect interrupt. 0 = normal operation. 1 = the line-side power supply has been disrupted. if the btdm bit (register 3) and inte bit (register 2) are set, a hardware interrupt occurs on the aout/int pin. this bit must be writ- ten to 0 to clear it. 3dodi drop out detect interrupt. 0 = normal operation. 1 = the line-side power supply has collapsed. (the dod bit in register 19 has fired.) if the dodm bit (register 3) and inte bit (register 2) are set, a hardware interrupt occurs on the aout/int pin. this bit must be written to 0 to be cleared. this bit should be cleared after clearing the pdl bit (register 6) as powering up the line-side device can cause this interrupt to be triggered. 2lcsoi loop current sense overload interrupt. 0 = normal operation. 1 = the lcs bits have reached max value. if the lcsom bit (register 3) and the inte bit are set, a hardware interrupt occurs on the aout/int pin. this bit must be written to 0 to clear it. note: lcsoi does not necessarily imply that an overcu rrent situation has occurred. an overcurrent situation in the daa is determined by the status of the opd bit (register 19). after the lcsoi interrupt fires, the opd bit should be checked to determine if an overcurrent situation exists.
si3050 + si3011 rev. 1.11 59 1tgdi tip ground detect interrupt. this bit is reverse logic as compared to the tgd bit. 0 = the co has not grounded tip causing current to flow. 1 = the co has grounded tip, causing current to flow. once set, this bit must be written to 0 to clear it. if the tdgm bit (register 3) and inte bit (register 3) are set, a hardware interrupt occurs on the aout/int pin. to clear the interr upt, write this bit to 0. 0poli polarity reversal detect interrupt. 0 = bit 7 of the lvs register has not changed states. 1 = bit 7 of the lvs register has tr ansitioned from 0 to 1, or from 1 to 0, indicating the polarity of tip and ring is switched. if the polm bit (register 3) and inte bit (register 2) are set, a hardware interrupt oc curs on the aout/int pin. to clear the interrupt, write this bit to 0. bit name function
si3050 + si3011 60 rev. 1.11 reset settings = 0000_0000 register 5. daa control 1 bit d7d6d5d4d3d2d1d0 name rdtn rdtp onhm rdt oh type r r r/w r r/w bit name function 7 reserved read returns zero. 6 rdtn ring detect signal negative. 0 = no negative ring signal is occurring. 1 = a negative ring signal is occurring. 5rdtp ring detect signal positive. 0 = no positive ring signal is occurring. 1 = a positive ring signal is occurring. 4 reserved read returns zero. 3 onhm on-hook line monitor. 0 = normal on-hook mode. 1 = enables low-power on-hook monitoring mode allowing the host to receive line activity without going off-hook. this mode is used for caller-id detection. 2 rdt ring detect. 0 = reset 5 seconds after last positive ring is detected or when the system executes an off-hook. only a positive ring sets this bit when rfwe = 0. when rfwe = 1, either a positive or negative ring sets this bit. 1 = indicates a ring is occurring. 1 reserved read returns zero. 0oh off-hook. 0 = line-side device on-hook. 1 = causes the line-side device to go off-hook.
si3050 + si3011 rev. 1.11 61 reset settings = 0001_0000 reset settings = 0000_0000 register 6. daa control 2 bit d7d6d5d4d3d2d1d0 name pdl pdn type r/w r/w bit name function 7:5 reserved read returns zero. 4pdl powerdown line-side device. 0 = normal operation. program the clock generator before clearing this bit. 1 = places the line-side device in lower power mode. 3pdn powerdown system-side device. 0 = normal operation. 1 = powers down the system-s ide device. a pulse on reset is required to restore normal operation. 2:0 reserved read returns zero. register 7. sample rate control bit d7d6d5d4d3d2d1d0 name hssm type r/w bit name function 7:4 reserved read returns zero. 3hssm high-speed sampling mode. 0 = sample rate is 8 khz. 1 = sample rate is 16 khz. the pcm or the gc i highway continues to be at 8 khz; thus, twice as many samples are generated per devic e timeslot. samples are transmitted in adja- cent timeslots. 2:0 reserved read returns zero.
si3050 + si3011 62 rev. 1.11 reset settings = 0000_0000 reset settings = 0000_0000 register 8-9. reserved bit d7d6d5d4d3d2d1d0 name type bit name function 7:0 reserved read returns zero. register 10. daa control 3 bit d7d6d5d4d3d2d1d0 name ddl type r/w bit name function 7:1 reserved read returns zero. 0ddl digital data loopback. 0 = normal operation. 1 = takes data received on drx and loops it back out to dtx before the tx and rx filters. output data is identical to the input data.
si3050 + si3011 rev. 1.11 63 reset settings = xxxx_xxxx reset settings = 0000_0000 register 11. system-side and line-side device revision bit d7d6d5d4d3d2d1d0 name lsid[3:0] reva[3:0] type rr bit name function 7:4 lsid[3:0] line-side id bits. the line-side bits corresponding to the si3011 are 0100. 3:0 reva[3:0] system-side revision. four-bit value indicating the revision of the si3050 (system-side) device. register 12. line-side device status bit d7d6d5d4d3d2d1d0 name fdt lcs[4:0] type rr bit name function 7 reserved read returns zero. 6fdt frame detect. 0 = indicates isocap link has not established frame lock. 1 = indicates isocap link frame lock is established. 5 reserved read returns zero. 4:0 lcs[4:0] off-hook loop current monitor (3.3 ma/bit). 00000 = loop current is less than required for normal operation. 00100 = minimum loop current for normal operation. 11111 = loop current is >127 ma, and an overload condition may exist.
si3050 + si3011 64 rev. 1.11 reset settings = xxxx_xxxx reset settings = 0000_0000 register 13. line-side device revision bit d7d6d5d4d3d2d1d0 name 1 revb[3:0] type rr bit name function 7 reserved read returns zero. 6 reserved this bit always reads a one. 5:2 revb[3:0] line-side device revision. four-bit value indicating the revision of the line-side device. 1:0 reserved read returns zero. register 14. daa control 4 bit d7d6d5d4d3d2d1d0 name rpol type r/w bit name function 7:2 reserved read returns zero. 1rpol ring detect polarity. 0 = the rgdt pin is active low. 1 = the rgdt pin is active high. 0 reserved read returns zero.
si3050 + si3011 rev. 1.11 65 reset settings = 0000_0000 reset settings = 0000_0000 register 15. tx/rx gain control 1 bit d7d6d5d4d3d2d1d0 name txm rxm type r/w r/w bit name function 7txm transmit mute. 0 = transmit signal is not muted. 1 = mutes the transmit signal. 6:4 reserved read returns zero. 3rxm receive mute. 0 = receive signal is not muted. 1 = mutes the receive signal. 2:0 reserved read returns zero. register 16. inte rnational control 1 bit d7d6d5d4d3d2d1d0 name iire type r/w bit name function 7:5 reserved these bits may be written to a zero or one. 4iire iir filter enable. 0 = fir filter enabled for transmit and receive filters. (see figures 7?10 on page 15.) 1 = iir filter enabled for transmit and receive filters. (see figures 11?16 on page 16.) 3:0 reserved these bits may be written to a zero or one.
si3050 + si3011 66 rev. 1.11 reset settings = 0000_0000 register 17. inte rnational control 2 bit d7d6d5d4d3d2d1d0 name calz mcal cald 0 ope bte rov btd type r/w r/w r/w r/w r/w r/w r bit name function 7calz clear adc calibration. 0 = normal operation. 1 = clears the existing adc calibration data. this bit must be written back to 0 after being set. 6 mcal manual adc calibration. 0 = no calibration. 1 = initiate manual adc calibration. 5cald auto-calibration disable. 0 = enable auto-calibration. 1 = disable auto-calibration. 4 reserved always write this bit to zero. 3ope overload protect enable. 0=disabled. 1 = enabled. the ope bit should always be cleared before going off-hook. 2bte billing tone detect enable. the daa can detect events, such as billing tones, that can cause a disruption in the line-side power supply. when this bit is set, the device will maintain off-hook during such events. if a billing tone is detected, the btd bit (register 17, bit 0) is set to indicate the event. writing this bit to zero clears the btd bit. 0 = billing tone detection disabled . the btd bit is not functional. 1 = billing tone detection enabled. the btd bi t is not functional. 1rov receive overload. this bit is set when the receive input has an excessive input level (i.e., receive pin goes below ground). writing a 0 to this location clears th is bit and the rovi bit (register 4, bit 6). 0 = normal receive input level. 1 = excessive receive input level. 0btd billing tone detected. this bit is set if an event, such as a billing tone, causes a disruption in the line-side power supply. writing a zero to bte clears this bit. 0 = no billing tone detected. 1 = billing tone detected.
si3050 + si3011 rev. 1.11 67 reset settings = 0000_0000 register 18. inte rnational control 3 bit d7d6d5d4d3d2d1d0 name rfwe type r/w bit name function 7:3 reserved read returns zero. 2 reserved this bit may be written to a zero or one. 1rfwe ring detector full-wave rectifier enable. when rngv (register 24) is disabled, this bit controls the ring detector mode and the asser- tion of the rgdt pin. when rngv is enabled, this bit configures the rgdt pin to either follow the ringing signal detected by the ring validation circuit, or to follow an unqualified ring detect one-shot signal initiated by a ri ng-threshold crossing and termin ated by a fixed counter timeout of approximately 5 seconds. rngv rfwe rgdt 0 0 half-wave 0 1 full-wave 1 0 validated ring envelope 1 1 ring threshold crossing one-shot 0 reserved read returns zero.
si3050 + si3011 68 rev. 1.11 reset settings = 0000_0000 register 19. inte rnational control 4 bit d7d6d5d4d3d2d1d0 name ovl dod opd type rrr bit name function 7:3 reserved read returns zero. 2ovl receive overload detect. this bit has the same function as rov (register 17 ), but clears itself after the overload is removed. see ?5.22.receive overload detection? on page 28. this bit is only masked by the off-hook counter and is not affected by the bte bit. 0 = normal receive input level. 1 = excessive receive input level. 1dod recal/dropout detect. when the line-side device is of f-hook, it is powered from the line itself. this bit will read 1 when loop current is not flowing. for example, if this line-derived power supply collapses, such as when the line is disconnected, this bit is set to 1. additionally, when on-hook, and the line-side device is enabled, this bit is set to 1. 0 = normal operation. 1 = line supply dropout detected when off-hook. 0opd overload protect detect. this bit is used to indicate that the daa has de tected a loop current overload. the detector fir- ing threshold depends on the setting of the ilim bit (register 26). opd ilim overcurrent threshold overcurrent status 0 0 160 ma no overcurrent condition exists 0 1 60 ma no overcurrent condition exists 1 0 160 ma overcurrent condition has been detected 1 1 60 ma overcurrent condition has been detected
si3050 + si3011 rev. 1.11 69 reset settings = 0000_0000 reset settings = 0000_0000 register 20. call progr ess rx attenuation bit d7d6d5d4d3d2d1d0 name arm[7:0] type r/w bit name function 7:0 arm[7:0] aout receive path attenuation. when decremented from the default setting, these bits linearly attenuate the aout receive path signal used for call progress monitoring. setting the bits to all 0s mutes the aout receive path. attenuation = 20 log(arm[7:0]/64) 1111_1111 = +12 db (gain) 0111_1111 = +6 db (gain) 0100_0000 = 0 db 0010_0000 = ?6 db (attenuation) 0001_0000 = ?12 db ... 0000_0000 = mute register 21. call progress tx attenuation bit d7d6d5d4d3d2d1d0 name atm[7:0] type r/w bit name function 7:0 atm[7:0] aout transmit pa th attenuation. when decremented from the default settings, these bits linearly attenuate the aout trans- mit path signal used for call progress monitori ng. setting the bits to all 0s mutes the aout transmit path. attenuation = 20 log(atm[7:0]/64) 1111_1111 = +12 db (gain) 0111_1111 = +6 db (gain) 0100_0000 = 0 db 0010_0000 = ?6 db (attenuation) 0001_0000 = ?12 db ... 0000_0000 = mute
si3050 + si3011 70 rev. 1.11 reset settings = 1001_0110 register 22. ring validation control 1 bit d7d6d5d4d3d2d1d0 name rdly[1:0] rmx[5:0] type r/w r/w bit name function 7:6 rdly[1:0] ring delay bits 1 and 0. these bits, in combination with the rdly[2] bit (register 23), set the amount of time between when a ring signal is validated and when a valid ring signal is indicated. rdly[2] rdly[1:0] delay 0000ms 001256ms 010512ms ... 1111792ms 5:0 rmx[5:0] ring assertion maximum count. these bits set the maximum ring frequency for a valid ring signal within a 10% margin of error. during ring qualification, a timer is load ed with the ras[5:0] field upon a tip/ring event and decrements at a regular rate. when a subsequent tip/ring event occurs, the timer value is compared to the rmx[5:0] field and if it exceeds the value in rmx[5:0] then the frequency of the ring is too high and th e ring is invalidated. the difference between ras[5:0] and rmx[5:0] identifies the minimum duration between tip/ring events to qual- ify as a ring, in binary-coded increments of 2.0 ms (nominal). a tip/ring event typically occurs twice per ring tone period. at 20 hz, tip/ring events would occur every 1/ (2 x 20 hz) = 25 ms. to calculate the correct rm x[5:0] value for a frequency range [f_min, f_max], the following equation should be used: to compensate for error margin and ensure a suff icient ring detection window, it is recom- mended that the calculated value of rmx[5:0] be incremented by 1. rmx 5:0 ?? ras 5:0 ?? 1 2 f_max ? 2 ms ? -------------------------------------------- - rmx ras ? ? ? ?
si3050 + si3011 rev. 1.11 71 reset settings = 0010_1101 register 23. ring validation control 2 bit d7 d6d5d4d3d2d1d0 name rdly[2] rto[3:0] rcc[2:0] type r/w r/w r/w bit name function 7 rdly[2] ring delay bit 2. this bit, in combination with the rdly[1:0] bits (register 22), sets the amount of time between when a ring signal is validated and when a valid ring signal is indicated. rdly[2] rdly[1:0] delay 0 00 0 m s 001256 m s 010512 m s ... 1111792 m s 6:3 rto[3:0] ring timeout. these bits set when a ring signal is determin ed to be over after the most recent ring threshold crossing. rto[3:0] ring timeout 0000 do not use this setting 0001 128 m s 0010 256 m s ... 1111 1920 m s 2:0 rcc[2:0] ring confirmation count. these bits set the amount of time that the ring frequency must be within the tolerances set by the ras[5:0] bits and the rmx[5:0] bits to be classified as a valid ring signal. rcc[2:0] ring confirmation count time 000 100 m s 001 150 m s 010 200 m s 011 256 m s 100 384 m s 101 512 m s 110 640 m s 111 1024 m s
si3050 + si3011 72 rev. 1.11 reset settings = 0001_1001 reset settings = xx0x_xxxx register 24. ring validation control 3 bit d7d6d5d4d3d2d1d0 name rngv ras[5:0] type r/w r/w bit name function 7rngv ring validation enable. 0 = ring validation feature is disabled. 1 = ring validation feature is enabled in both normal operating mode and low-power mode. 6 reserved always write these bits to zero. 5:0 ras[5:0] ring assertion time. these bits set the minimum ring frequency for a valid ring signal. during ring qualification, a timer is loaded with the ras[5:0] field upo n a tip/ring event and decrements at a reg- ular rate. if a second or subsequent tip/ring event occurs after the timer has timed out then the frequency of the ring is too low and the ring is invalidated. the difference between ras[5:0] and rmx[5:0] identifies the minimum duration between tip/ring events to qual- ify as a ring, in binary-coded increments of 2.0 ms (nominal). a tip/ring event typically occurs twice per ring tone period. at 20 hz, tip/ring events would occur every 1/(2 x 20 hz) = 25 ms. to calculate the corr ect ras[5:0] value for a frequency range [f_min, f_max], the following equation should be used: register 25. resistor calibration bit d7d6d5d4d3d2d1d0 name rcals rcalm rcald rcal[3:0] type rr/wr/w r/w bit name function 7 rcals resistor auto calibration. 0 = resistor calibration is not in progress. 1 = resistor calibration is in progress. 6 rcalm manual resistor calibration. 0 = no calibration. 1 = initiate manual resistor calibration. (after a manual calibration has been initiated, this bit must be cleared within 1 ms.) 5 rcald resistor calibration disable. 0 = internal resistor calibration enabled. 1 = internal resistor calibration disabled. 4 reserved this bit can be written to a 0 or 1. 3:0 rcal[3:0] always write back the value read. ras 5:0 ?? 1 2f_min ? 2 ms ? ------------------------------------------- ?
si3050 + si3011 rev. 1.11 73 reset settings = 0000_0000 register 26. dc termination control bit d7d6d5d4d3d2d1d0 name 0 0 ilim dcr type r/w r/w bit name function 7:4 reserved these bits may be written to a zero or one. 3:2 reserved always write these bits to zero. 1 ilim current limiting enable. 0 = current limiting mode disabled. 1 = current limiting mode enabled. this mode limits loop current to a maximum of 60 ma per the tbr21 standard. 0 dcr dc impedance selection. 0=50 ? dc termination is selected. this mode shou ld be used for all standard applications. 1 = 800 ? dc terminatio n is selected.
si3050 + si3011 74 rev. 1.11 reset settings = xxxx_xxxx reset settings = 0000_0000 reset settings = 0000_0000 register 27. reserved bit d7d6d5d4d3d2d1d0 name type bit name function 7:0 reserved do not write to these register bits. register 28. loop current status bit d7d6d5d4d3d2d1d0 name lcs2[7:0] type r bit name function 7:0 lcs2[7:0] loop current status. eight-bit value returning the loop current. each bit represents 1.1 ma of loop current. 0000_0000 = loop current is less than required for normal operation. register 29. line voltage status bit d7d6d5d4d3d2d1d0 name lvs[7:0] type r bit name function 7:0 lvs[7:0] line voltage status. eight-bit value returning the loop voltage. each bit represents 1 v of loop voltage. this regis- ter operates in on- and off-hook modes. bit seven of this register indicates the polarity of the tip/ring voltage. when this bit changes state, it indicates that a polarity reversal has occurred. the value returned is represented in 2s complement format. 0000_0000 = no line is connected.
si3050 + si3011 rev. 1.11 75 reset settings = 0000_0000 register 30. ac termination control bit d7d6d5d4d3d2d1d0 name full20 0acim0 type r/w r/w bit name function 7:6 reserved read returns zero. 5 reserved this bit may be written to a zero or one. 4 full2 enhanced full scale (2x) transmit and receive mode. 0=default 1 = transmit/receive 2x full scale this bit changes the full scale of the adc and dac from 0 min to +6 dbm into 600 ? load (or 1.5 dbv into all reference impedances). when this bit is set, low loop currents may result in increased distortion. 3:2 reserved always write these bits to zero. 1 acim ac impedance selection. the off-hook ac termination is selected from the following: 0 = 600 ? 1 = 270 ? + (750 ?? || 150 nf) and 275 ?? + (780 ?? || 150 nf) 0 reserved always write this bit to zero.
si3050 + si3011 76 rev. 1.11 reset settings = 0010_0000 register 31. daa control 5 bit d7d6d5d4d3d2d1d0 name 0 foh[1:0] 0 ohs2 0 filt lvfd type rw r/w r/w r/w bit name function 7 reserved always write this bit to zero. 6:5 foh[1:0] fast off-hook selection. these bits determine the length of the off-hook counter. the default setting is 128 ms. 00 = 512 ms 01 = 128 ms 10 = 64 ms 11 = 8 ms 4 reserved always write this bit to zero. 3 ohs2 on-hook speed 2. this bit sets the on-hook transition speed. on-hook speeds specified are measured from the time the oh bit is cleared until loop current equals zero. ohs2 mean on-hook speed 0 less than 0.5 ms 1 3 ms 10% (meets etsi standard) 2 reserved always write these bits to zero. 1filt filter pole selection. 0 = the receive path has a low ?3 dbfs corner at 5 hz. 1 = the receive path has a low ?3 dbfs corner at 200 hz. 0lvfd line voltage force disable. 0 = normal operation. 1 = the circuitry that forces the lvs register (regis ter 29) to all 0s at 3 v or less is disabled. the lvs register may display unpredictable values at voltages between 0 to 2 v. all 0s are displayed if the line voltage is 0 v.
si3050 + si3011 rev. 1.11 77 reset settings = 0000_0x11 register 32. ground start control bit d7d6d5d4d3d2d1d0 name tgd tgde rg type rww bit name function 7:3 reserved read returns zero. 2tgd tip ground detect. 0 = the co has grounded tip, causing current to flow. when current ceases to flow, this bit returns to a one. 1 = the co has not grounded tip causing current to flow. 1tgde tip ground detect enable. 0 = the external relay connecting tip to an isolat ed supply is closed, enabling current to flow in tip if the co grounds tip. 1 = the external relay connecting tip to an isolat ed supply is open. in this state, the daa is unable to determine if the co has grounded tip. 0rg ring ground. 0 = the external relay connecting ring to ground is closed, causing current to flow in ring. 1 = the external relay connecting ring to ground is open, not allowing current to flow in ring.
si3050 + si3011 78 rev. 1.11 reset settings = 0000_0000 register 33. pcm/ spi mode select bit d7d6d5d4d3d2d1d0 name pcml pcme pcmf[1:0] 0 phcf tri type r/w r/w r/w r/w r/w r/w r/w bit name function 7 pcml pcm analog loopback. 0 = normal operation. 1 = enables analog data to be received from th e line, converted to digital data and trans- mitted across the isocap link. the data passes through the rx filter and is looped back through the tx filter and is transmitted back out to the line. 5pcme pcm enable (registers 34?37 should be set before pcm transfers are enabled). 0 = disable pcm transfers. 1 = enable pcm transfers. 4:3 pcmf[1:0] pcm data format. 00 = a-law. signed magnitude data format (refer to table 20 on page 39). 01 = -law. signed magnitude data format (refer to table 19 on page 38). 10 = 8-bit linear. the top 8-bits of the 16-bit linear signal are transferred, and the bottom 8-bits are discarded (2s complement data format). 11 = 16-bit linear (2s complement data format). 2 reserved always writ e this bit to zero. 1phcf pcm highway clock format. 0 = 1 pclk per data bit. 1 = 2 pclks per data bit. 0tri tri-state bit 0. 0 = tri-state bit 0 on positive edge of pclk. 1 = tri-state bit 0 on negative edge of pclk.
si3050 + si3011 rev. 1.11 79 reset settings = 0000_0000 reset settings = 0000_0000 reset settings = 0000_0000 register 34. pcm transmit start count?low byte bit d7d6d5 d4 d3d2 d1 d0 name txs[7:0] type r/w bit name function 7:0 txs[7:0] pcm transmit start count. pcm transmit start count equals the number of pclks following fsync before data transmission begins. register 35. pcm transmit start count?high byte bit d7d6d5d4d3d2d1d0 name txs[1:0] type r/w bit name function 7:2 reserved read returns zero. 1:0 txs[1:0] pcm transmit start count. pcm transmit start count equals the number of pclks following fsync before data transmission begins. register 36. pcm receive start count?low byte bit d7d6d5d4d3d2d1d0 name rxs[7:0] type r/w bit name function 7:0 rxs[7:0] pcm receive start count. pcm receive start count equals the number of pclks following fsync before data reception begins.
si3050 + si3011 80 rev. 1.11 reset settings = 0000_0000 reset settings = 0000_0000 register 37. pcm receive start count?high byte bit d7d6d5d4d3d2d1d0 name rxs[1:0] type r/w bit name function 7:2 reserved read returns zero. 1:0 rxs[1:0] pcm receive start count. pcm receive start count equals the number of pclks following fsync before data reception begins. register 38. tx gain control 2 bit d7d6d5d4d3d2d1d0 name tga2 txg2[3:0] type r/w r/w bit name function 7:5 reserved read returns zero. 4tga2 transmit gain or attenuation 2. 0 = incrementing the txg2[3:0] bits results in gaining up the transmit path. 1 = incrementing the txg2[3:0] bits results in attenuating the transmit path. 3:0 txg2[3:0] transmit gain 2. each bit increment represents 1 db of gain or attenuation, up to a maximum of +12 db and ?15 db respectively. for example: tga2 txg2[3:0] result x 0000 0 db gain or attenuation is applied to the transmit path. 0 0001 1 db gain is applied to the transmit path. 0 : 0 11xx 12 db gain is applied to the transmit path. 1 0001 1 db attenuation is applied to the transmit path. 1 : 1 1111 15 db attenuation is applied to the transmit path.
si3050 + si3011 rev. 1.11 81 reset settings = 0000_0000 register 39. rx gain control 2 bit d7d6d5d4d3d2d1d0 name rga2 rxg2[3:0] type r/w r/w bit name function 7:5 reserved read returns zero. 4rga2 receive gain or attenuation 2. 0 = incrementing the rxg2[3:0] bits results in gaining up the receive path. 1 = incrementing the rxg2[3:0] bits results in attenuating the receive path. 3:0 rxg2[3:0] receive gain 2. each bit increment represents 1 db of gain or attenuation, up to a maximum of +12 db and ?15 db respectively. for example: rga2 rxg2[3:0] result x 0000 0 db gain or attenuation is applied to the receive path. 0 0001 1 db gain is applied to the receive path. 0 : 0 11xx 12 db gain is applied to the receive path. 1 0001 1 db attenuation is applied to the receive path. 1 : 1 1111 15 db attenuation is applied to the receive path.
si3050 + si3011 82 rev. 1.11 reset settings = 0000_0000 register 40. tx gain control 3 bit d7d6d5d4d3d2d1d0 name tga3 txg3[3:0] type r/w r/w bit name function 7:5 reserved read returns zero. 4tga3 transmit gain or attenuation 3. 0 = incrementing the tga3[3:0] bits results in gaining up the transmit path. 1 = incrementing the tga3[3:0] bits results in attenuating the transmit path. 3:0 txg3[3:0] transmit gain 3. each bit increment represents 0.1 db of gain or attenuation, up to a maximum of 1.5 db. for example: tga3 txg3[3:0] result x 0000 0 db gain or attenuation is applied to the transmit path. 0 0001 0.1 db gain is applied to the transmit path. 0 : 0 1111 1.5 db gain is appli ed to the transmit path. 1 0001 0.1 db attenuation is applied to the transmit path. 1 : 1 1111 1.5 db attenuation is applied to the transmit path.
si3050 + si3011 rev. 1.11 83 reset settings = 0000_0000 register 41. rx gain control 3 bit d7d6d5d4d3d2d1d0 name rga3 rxg3[3:0] type r/w r/w bit name function 7:5 reserved read returns zero. 4rga3 receive gain or attenuation 2. 0 = incrementing the rxg3[3:0] bits results in gaining up the receive path. 1 = incrementing the rxg3[3:0] bits results in attenuating the receive path. 3:0 rxg3[3:0] receive gain 3. each bit increment represents 0.1 db of gain or attenuation, up to a maximum of 1.5 db. for example: rga3 rxg3[3:0] result x 0000 0 db gain or attenuation is applied to the receive path. 0 0001 0.1 db gain is applied to the receive path. 0 : 0 1111 1.5 db gain is applied to the receive path. 1 0001 0.1 db attenuation is applied to the receive path. 1 : 1 1111 1.5 db attenuation is applied to the receive path.
si3050 + si3011 84 rev. 1.11 reset settings = 0000_0000 register 42. gci control bit d7d6d5d4 d3 d2 d1 d0 name gcif[1:0] b2d b1d type r/w r/w r/w bit name function 7:4 reserved read returns zero. 3:2 gcif[1:0] gci data format. 00 = a-law. 01 = -law. 10 = 8-bit linear. the top 8-bits of the 16-bit linear signal are transferred, and the bottom 8-bits are discarded. 11 = 16-bit linear. b1 and b2 channels are used for the 16-bits of data. regardless of whether the daa is set to transmit and receive in the b1 or b2 channel, both channels are used to send and receive the 16-bit linear data. 1b2d channel b2 enable. 0 = channel b2 transfers are disabled. 1 = channel b2 transfers are enabled. if 16-bit linear data format is chosen, disabling the b2 channel results in only the top 8 bits of line data being sent and received in the b1 channel. 0b1d channel b1 enable. 0 = channel b1 transfers are disabled. 1 = channel b1 transfers are enabled. if 16-bit linear data format is chosen, disabling the b1 channel results in only the bottom 8 bits of line data being sent and received in the b2 chan- nel.
si3050 + si3011 rev. 1.11 85 reset settings = 0000_0000 reset settings = 0000_0000 register 43. line current/voltage threshold interrupt bit d7d6d5d4d3d2d1d0 name cvt[7:0] type r/w bit name function 7:0 cvt[7:0] current/voltage threshold. these bits determine the threshold at which an interrupt is generated from either the lcs or lvs register. this interrupt can be generated to occur when the line current or line voltage rises above or drops below the value in the cvt[7:0] register. register 44. line current/voltage threshold interrupt control bit d7d6d5d4d3d2d1d0 name cvi cvs cvm cvp type r/w r/w r/w r/w bit name function 7:4 reserved read returns zero. 3cvi current/voltage interrupt. 0 = the current/voltage threshold has not been crossed. 1 = the current/voltage threshold is crossed. if the cvm and inte bits are set, a hardware interrupt occurs on the aout/int pin. once set, this bit must be written to 0 to be cleared. 2cvs current/voltage select. 0 = the line current shown in the lcs2 register is used to generate an interrupt. 1 = the line voltage shown in the lvs register is used to generate an interrupt. 1cvm current/voltage interrupt mask. 0 = the current/voltage threshold being triggered does not cause a hardware interrupt on the aout/int pin. 1 = the current/voltage threshold being triggered causes a hardware interrupt on the aout/int pin. 0cvp current/voltage interrupt polarity. 0 = the current/voltage threshold is triggered by the absolute value of the number in either the lcs2 or lvs register falling below the value in the cvt[7:0] register. 1 = the current/voltage threshold is triggered by the absolute value of the number in either the lcs2 or lvs register rising above the value in the cvt[7:0] register.
si3050 + si3011 86 rev. 1.11 reset settings = 0000_0000 reset settings = 0000_0000 register 45. programmable hybrid register 1 bit d7d6d5d4d3d2d1d0 name hyb1[7:0] type r/w bit name function 7:0 hyb1[7:0] programmable hybrid register 1. these bits can be programmed with a coefficien t value to adjust the hybrid response to reduce near-end echo. this register represents th e first tap in the eight-tap filter. when this register is set to all 0s, this filter stage does not have an effect on the hybrid response. see the section entitled "5.28. transhybrid balance" on page 32 for more information on selecting coefficients for the programmable hybrid. register 46. programmable hybrid register 2 bit d7d6d5d4d3d2d1d0 name hyb2[7:0] type r/w bit name function 7:0 hyb2[7:0] programmable hybrid register 2. these bits can be programmed with a coefficien t value to adjust the hybrid response to reduce near-end echo. this register represents the second tap in the eight-tap filter. when this register is set to all 0s, th is filter stage does not have an effect on the hybrid response. see the section entitled "5.28. transhybrid bala nce" on page 32 for more information on selecting coefficients for the programmable hybrid.
si3050 + si3011 rev. 1.11 87 reset settings = 0000_0000 reset settings = 0000_0000 register 47. programmable hybrid register 3 bit d7d6d5d4d3d2d1d0 name hyb3[7:0] type r/w bit name function 7:0 hyb3[7:0] programmable hybrid register 3. these bits can be programmed with a coefficien t value to adjust the hybrid response to reduce near-end echo. this register represents the third tap in the eight-tap filter. when this register is set to all 0s, this filter stage does not have an effect on the hybrid response. see the section entitled "5.28. transhybrid balance" on page 32 for more information on selecting coefficients for the programmable hybrid. register 48. programmable hybrid register 4 bit d7d6d5d4d3d2d1d0 name hyb4[7:0] type r/w bit name function 7:0 hyb4[7:0] programmable hybrid register 4. these bits can be programmed with a coefficien t value to adjust the hybrid response to reduce near-end echo. this register represents the fourth tap in the eight-tap filter. when this register is set to all 0s, this filter stage does not have an effect on the hybrid response. see the section entitled "5.28. transhybrid balance" on page 32 for more information on selecting coefficients for the programmable hybrid.
si3050 + si3011 88 rev. 1.11 reset settings = 0000_0000 reset settings = 0000_0000 register 49. programmable hybrid register 5 bit d7d6d5d4d3d2d1d0 name hyb5[7:0] type r/w bit name function 7:0 hyb5[7:0] programmable hybrid register 5. these bits can be programmed with a coefficien t value to adjust the hybrid response to reduce near-end echo. this register represents th e fifth tap in the eight-tap filter. when this register is set to all 0s, this filter stage does not have an effect on the hybrid response. see the section entitled "5.28. transhybrid balance" on page 32 for more information on selecting coefficients for the programmable hybrid. register 50. programmable hybrid register 6 bit d7d6d5d4d3d2d1d0 name hyb6[7:0] type r/w bit name function 7:0 hyb6[7:0] programmable hybrid register 6. these bits can be programmed with a coefficien t value to adjust the hybrid response to reduce near-end echo. this register represents the sixth tap in the eight-tap filter. when this register is set to all 0s, this filter stage does not have an effect on the hybrid response. see the section entitled "5.28. transhybrid balance" on page 32 for more information on selecting coefficients for the programmable hybrid.
si3050 + si3011 rev. 1.11 89 reset settings = 0000_0000 reset settings = 0000_0000 reset settings = xxxx_xxxx register 51. programmable hybrid register 7 bit d7d6d5d4d3d2d1d0 name hyb7[7:0] type r/w bit name function 7:0 hyb7[7:0] programmable hybrid register 7. these bits can be programmed with a coefficien t value to adjust the hybrid response to reduce near-end echo. this register represents the seventh tap in the eight-tap filter. when this register is set to all 0s, th is filter stage does not have an effect on the hybrid response. see the section entitled "5.28. transhybrid bala nce" on page 32 for more information on selecting coefficients for the programmable hybrid. register 52. programmable hybrid register 8 bit d7d6d5d4d3d2d1d0 name hyb8[7:0] type r/w bit name function 7:0 hyb8[7:0] programmable hybrid register 8. these bits can be programmed with a coefficien t value to adjust the hybrid response to reduce near-end echo. this register represents the eighth tap in the eight-tap filter. when this register is set to all 0s, this filter stage does not have an effect on the hybrid response. see the section entitled "5.28. transhybrid balance" on page 32 for more information on selecting coefficients for the programmable hybrid. register 53-58. reserved bitd7d6d5d4d3d2d1d0 name type bit name function 7:0 reserved do not write to these register bits.
si3050 + si3011 90 rev. 1.11 reset settings = xxxx_xxxx register 59. rx gain control 1 bitd7d6d5d4d3d2d1d0 name 00000rg1gce0 type r/w r/w bit name function 7:3 reserved always write these bits to zero. 2rg1 receive gain 1. this bit enables receive path gain adjustment. 0 = no gain applied to hybrid , full scale rx on line = 0 dbm. 1 = 1 db of gain applied to hybr id, full scale rx on line = ?1 dbm. 1gce guarded clear enable. this bit (in conjunction with the r2 bit set to 1) enables the si3050 to meet bt?s guarded clear spec (b5 6450, part 1: 1993, section 15.4 .3.3). with these bits set, the daa will draw approximately 2.5 ma of current from the line while on-hook. 0 = default, daa does not draw loop current. 1 = guarded clear enabled, daa draws 2.5 ma while on-hook to meet guarded clear requirement. 0 reserved always write this bit to zero.
si3050 + si3011 rev. 1.11 91 a ppendix ?iec/ul60950 3 rd e dition introduction although designs using the si3011 comply with iec/ ul60950 3rd edition and pass all overcurrent and overvoltage tests, there are still several issues to consider. figure 48 shows two designs that can pass the iec/ ul60950 overvoltage tests and electromagnetic emissions. the top schematic shows the configuration in which the ferrite beads (fb1, fb2) are on the unprotected side of the sidactor (rv1). for this configuration, the current rating of the ferrite beads needs to be 6 a. however, the higher current ferrite beads are less effective in reducing electromagnetic emissions. the bottom schematic of figure 48 shows the configuration in which the ferrite beads (fb1, fb2) are on the protected side of the sidactor (rv1). for this design, the ferrite beads can be rated at 200 ma. in a cost optimized design, it is important to remember that compliance to iec/ul60950 does not always require overvoltage tests. it is best to plan ahead and know which overvoltage test s applies to your system. system-level elements in th e construction, such as fire enclosure and spacing requirements, must be considered during the design stages. consult with your professional testing agency during the design of the product to determine which tests apply to your system. figure 48. circuits that pass all overvoltage tests rv1 rv1 fb1 fb2 tip ring tip ring fb1 fb2 75 ?? @ 100 mhz, 6 a 75 ?? @ 100 mhz, 6 a 600 ?? at 100 mhz, 200 ma 600 ?? at 100 mhz, 200 ma c9 1.25 a 1.25 a c9 c8 c8
si3050 + si3011 92 rev. 1.11 7. pin descriptions: si3050 table 23. si3050 pin descriptions pin # pin name description 1sdo serial port data output. serial port control data output. 2sdi serial port data input. serial port control data input. 3cs chip select input. an active low input control signal that e nables the spi serial port. when inactive, sclk and sdi are ignored and sdo is high impedance. 4fsync frame sync input. data framing signal that is used to indica te the start and stop of a communication/data frame. 5pclk master clock input. master clock input. 6dtx transmit pcm or gci highway data output. outputs data from either the pcm or gci highway bus. 7drx receive pcm or gci highway data input. receives data from either the pcm or gci highway bus. 8rgdt ring detect output. produces an active low rectified version of the ring signal. 9aout/int analog speaker output/interrupt output. provides an analog output signal for driv ing a call progress speaker in aout mode. alternatively, this pin can be set to provide a hardware interrupt signal. 10 rg ring ground output. control signal for ring ground relay. used to support ground start applications. 2 1 3 4 5 6 7 8 15 16 14 13 12 11 9 10 19 20 18 17 fsync sclk pclk sdi sdo aout/int rg dtx drx v a c1a c2a sdithru reset gnd tgde tgd cs rgdt v dd
si3050 + si3011 rev. 1.11 93 11 tgd tip ground detect input. used to detect current flowing in tip fo r supporting ground start applications. 12 tgde tip ground detect enable output. control signal for the ground detect relay. used to support ground start applications. 13 reset reset input. an active low input that is used to reset all control registers to a defined, initialized state. also used to bring the si3050 out of sleep mode. 14 c2a isolation capacitor 2a. connects to one side of the isolation capacitor c2. used to communicate with the line-side device. 15 c1a isolation capacitor 1a. connects to one side of the isolation capacitor c1. used to communicate with the line-side device. 16 v a regulator voltage reference. this pin connects to an external capacitor an d serves as the reference for the internal voltage regulator. 17 v dd digital supply voltage. provides the 3.3 v digital supply voltage to the si3050. 18 gnd ground. connects to the system digital ground. 19 sclk serial port bit clock input. controls the serial data on sdo and latches the data on sdi. 20 sdithru sdi passthrough output. cascaded sdi output signal to daisy-chain the spi interface with additional devices. table 23. si3050 pin descriptions (continued) pin # pin name description
si3050 + si3011 94 rev. 1.11 8. pin descriptions: si3011 pin # pin name description 1qe transistor emitter. connects to the emitter of q3. 2dct dc termination. provides dc termination to the telephone network. 3rx receive input. serves as the receive side input from the telephone network. 4ib internal bias. provides a bias voltage to the device. 5c1b isolation capacitor 1b. connects to one side of isolation capacitor c1. used to communicate with the system-side device. 6c2b isolation capacitor 2b. connects to one side of isolation capacitor c2. used to communicate with the system-side device. 7vreg voltage regulator. connects to an external capacitor to provide bypassing for an internal power supply. 8 rng1 ring 1. connects through a resistor to the tip lead of the telephone line. provides the ring and caller id signals to the daa. 9 rng2 ring 2. connects through a resistor to the ring lead of the telephone line. provides the ring and caller id signals to the daa. 10 vreg2 voltage regulator 2. connects to an external capacitor to provide bypassing for an internal power supply. 11 sc sc connection. enables external transistor network. should be tied through a 0 ? resistor to i gnd . 12 qe2 transistor emitter 2. connects to the emitter of q4. 13 qb transistor base. connects to the base of transistor q4. qe dct rx ib c1b c2b vreg rng1 dct2 dct3 qb qe2 sc vreg2 rng2 ignd 2 1 3 4 5 6 7 8 15 16 14 13 12 11 10 9
si3050 + si3011 rev. 1.11 95 14 dct3 dc termination 3. provides dc termination to the telephone network. 15 ignd isolated ground. connects to ground on the line-side interface. 16 dct2 dc termination 2. provides dc termination to the telephone network. pin # pin name description
si3050 + si3011 96 rev. 1.11 9. ordering guide 10. product identification the product identification number is a finished goods part number or is specified by a finished goods part number, such as a special customer part number. example: chipset region system-side (tssop) line-side (soic) line-side (tssop) pb-free and rohs-compliant temperature si3050+si3011 fcc/tbr21 si3050-e-ft si3011-f-fs si3011-f-ft yes 0 to +70 ? c si3050+si3011 fcc/tbr21 si3050-e-gt si3011-f-gs si3011-f-gt yes ?40 to +85 ? c note: refer to "10. product identification" on page 96 for more information on part naming conventions. si3050-e-fsr shipping option blank = tubes r = tape and reel product revision product designator package type s = soic t = tssop part type/lead finish f = commercial/lead-free g = industrial temp/lead-free
si3050 + si3011 rev. 1.11 97 11. package outline: 20-pin tssop figure 49 illustrates the package details for the si3050. table 24 lists the va lues for the dimensions shown in the illustration. figure 49. 20-pin thin shrink small outline package (tssop)
si3050 + si3011 98 rev. 1.11 table 24. 20-pin tssop package diagram dimensions dimension min nom max a??1.20 a1 0.05 ? 0.15 a2 0.80 1.00 1.05 b 0.19 ? 0.30 c 0.09 ? 0.20 d 6.40 6.50 6.60 e 6.40 bsc e1 4.40 4.40 4.50 e 0.65 bsc l 0.45 0.60 0.75 l2 0.25 bsc 0 ? 8 aaa 0.10 bbb 0.10 ccc 0.20 notes: 1. all dimensions shown are in mill imeters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. this drawing conforms to the jedec solid state outline mo-153, variation ac. 4. recommended card reflow profile is per the jedec/ipc j-std-020c specification for small body components.
si3050 + si3011 rev. 1.11 99 12. package outline: 16-pin soic figure 50 illustrates the packag e details for the si3011. table 25 lists the values for the dimens ions shown in the illustration. figure 50. 16-pin small outline inte grated circuit (soic) package
si3050 + si3011 100 rev. 1.11 table 25. 16-pin soic package diagram dimensions dimension min max a ? 1.75 a1 0.10 0.25 a2 1.25 ? b 0.31 0.51 c 0.17 0.25 d 9.90 bsc e 6.00 bsc e1 3.90 bsc e 1.27 bsc l 0.40 1.27 l2 0.25 bsc h 0.25 0.50 0 8 aaa 0.10 bbb 0.20 ccc 0.10 ddd 0.25 notes: 1. all dimensions shown are in millim eters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. this drawing conforms to the jedec solid state outline ms-012, variation ac. 4. recommended card reflow profile is per the jedec/ipc j-std-020c specification for small body components.
si3050 + si3011 rev. 1.11 101 13. package outline: 16-pin tssop figure 51 illustrates the packag e details for the si3011. table 26 lists the values for the dimens ions shown in the illustration. figure 51. 16-pin thin shrink small outline package (tssop)
si3050 + si3011 102 rev. 1.11 table 26. 16-pin tssop package diagram dimensions dimension min nom max a??1.20 a1 0.05 ? 0.15 a2 0.80 1.00 1.05 b 0.19 ? 0.30 c 0.09 ? 0.20 d 4.90 5.00 5.10 e 6.40 bsc e1 4.40 4.40 4.50 e 0.65 bsc l 0.45 0.60 0.75 l2 0.25 bsc 0 ? 8 aaa 0.10 bbb 0.10 ccc 0.20 notes: 1. all dimensions shown are in millimeters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. this drawing conforms to the jedec solid state outline mo-153, variation ab. 4. recommended card reflow profile is per the jedec/ipc j-std-020c specification for small body components.
si3050 + si3011 rev. 1.11 103 s ilicon l abs si3050 s upport d ocumentation ? an16: multiple device support ? an17: designing for international safety compliance ? an30: ground start impl ementation with silic on laboratories? daas ? an67: layout guidelines ? an72: ring detection/validation with the si305x daas ? an77: silicon daa software guidelines (si3050) ? an81: emissions design considerations ? an84: digital hybrid with the si305x daas note: refer to www.silabs.com for a current list of support documents for this chipset.
si3050 + si3011 104 rev. 1.11 n otes :
si3050 + si3011 rev. 1.11 105 d ocument c hange l ist revision 1.0 to revision 1.1 ? updated deep sleep total supply current from 1.0 to 1.3 ma typical ? updated package pictures ? removed all spim references (spim bit is never present in any si3050 device). ? removed snpb package options ? minor typo corrections revision 1.1 to revision 1.11 ? the internal system-side revision value (reva[3:0] in register 11) has been incremented by one for si3050 revision e.
si3050 + si3011 106 rev. 1.11 c ontact i nformation silicon laboratories inc. 400 west cesar chavez austin, tx 78701 tel: 1+(512) 416-8500 fax: 1+(512) 416-9669 toll free: 1+(877) 444-3032 email: sidaainfo@silabs.com internet: www.silabs.com silicon laboratories and silicon labs are trademarks of silicon laboratories inc. other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. the information in this document is believ ed to be accurate in all respects at the time of publication but is subject to change without notice. silicon laboratories assumes no responsibility for errors and omissions, and disclaims responsib ility for any consequences resu lting from the use of information included herein. a dditionally, silicon laboratorie s assumes no responsibility for the functioning of und escribed features or parameters. silicon laboratories reserves the right to make changes without further notice . silicon laboratories makes no wa rranty, rep- resentation or guarantee regarding the suitability of its products for any particular purpose, nor does silicon laboratories as sume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any an d all liability, including wi thout limitation conse- quential or incidental damages. silicon laborat ories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the silicon labor atories product could create a s ituation where per- sonal injury or death may occur. should buyer purchase or us e silicon laboratories products for any such unintended or unauthor ized ap- plication, buyer shall indemnify and hold silicon laboratories harmless against all claims and damages.

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